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ISCAS
1995
IEEE
83views Hardware» more  ISCAS 1995»
14 years 5 days ago
Analog Filter Banks with Low Intermodulation Distortion
It is demonstrated that the filter-bank structure of [1] can be designed to significantly reduce the effect of intermodulation distortion. This gives it an important advantage o...
James A. Cherry, W. Martin Snelgrove
ISCAS
1995
IEEE
107views Hardware» more  ISCAS 1995»
14 years 5 days ago
Power Dissipation in Deep Submicron CMOS Digital Circuits
— This paper introduces a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circuits. The model is based on Berkeley S...
R. X. Gu, Mohamed I. Elmasry
ISCAS
1995
IEEE
74views Hardware» more  ISCAS 1995»
14 years 5 days ago
Application of Fast Orthogonal Search for the Design of RBFNN
Wahid Ahmed, Donald M. Hummels, Mohamad T. Musavi
ISCA
1995
IEEE
121views Hardware» more  ISCA 1995»
14 years 5 days ago
A Comparative Analysis of Schemes for Correlated Branch Prediction
Modern high-performance architectures require extremely accurate branch prediction to overcome the performance limitations of conditional branches. We present a framework that cat...
Cliff Young, Nicholas C. Gloy, Michael D. Smith
ISCA
1995
IEEE
98views Hardware» more  ISCA 1995»
14 years 5 days ago
Instruction Fetching: Coping with Code Bloat
Previous research has shown that the SPEC benchmarks achieve low miss ratios in relatively small instruction caches. This paper presents evidence that current software-development...
Richard Uhlig, David Nagle, Trevor N. Mudge, Stuar...
ISCA
1995
IEEE
93views Hardware» more  ISCA 1995»
14 years 5 days ago
Optimizing Memory System Performance for Communication in Parallel Computers
Communicationin aparallel systemfrequently involvesmoving data from the memory of one node to the memory of another; this is the standard communication model employedin message pa...
Thomas Stricker, Thomas R. Gross
ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
14 years 5 days ago
Instruction Cache Fetch Policies for Speculative Execution
Current trends in processor design are pointing to deeper and wider pipelines and superscalar architectures. The efficient use of these resources requires speculative execution, ...
Dennis Lee, Jean-Loup Baer, Brad Calder, Dirk Grun...
ISCA
1995
IEEE
147views Hardware» more  ISCA 1995»
14 years 5 days ago
Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors
This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache coherence overhead in shared-memory multiprocessors. DSI eliminates invalidation messages...
Alvin R. Lebeck, David A. Wood