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ASPDAC
2001
ACM
59views Hardware» more  ASPDAC 2001»
14 years 9 days ago
Module placement with boundary constraints using the sequence-pair representation
Jianbang Lai, Ming-Shiun Lin, Ting-Chi Wang, Li-C....
ASAP
2003
IEEE
112views Hardware» more  ASAP 2003»
14 years 9 days ago
Comparison of Branching CORDIC Implementations
In this paper we compare implementations of Duprat and Muller's Branching CORDIC and Phatak's Double Step Branching (DSB)
Abhishek Singh, Dhananjay S. Phatak, Tom Goff, Mik...
ASPDAC
2001
ACM
102views Hardware» more  ASPDAC 2001»
14 years 9 days ago
New graph bipartizations for double-exposure, bright field alternating phase-shift mask layout
Abstract-- We describe new graph bipartization algorithms for layout modification and phase assignment of bright-field alternating phaseshifting masks (AltPSM) [25]. The problem of...
Andrew B. Kahng, Shailesh Vaya, Alexander Zelikovs...
ASAP
2003
IEEE
91views Hardware» more  ASAP 2003»
14 years 9 days ago
Reconfigurable Computing and Electronic Nanotechnology
Seth Copen Goldstein, Mihai Budiu, Mahim Mishra, G...
ASAP
2003
IEEE
99views Hardware» more  ASAP 2003»
14 years 9 days ago
Using Group Theory to Specify Application Specific Interconnection Networks for SIMD DSPs
We introduce another view of group theory in the field of interconnection networks. With this approach it is possible to specify application specific network topologies for permut...
Thorsten Dräger, Gerhard Fettweis
ASPDAC
2001
ACM
82views Hardware» more  ASPDAC 2001»
14 years 9 days ago
Reusable embedded in-circuit emulator
In this paper, we o introduce the Reusable Embedded In-Circuit Emulator (EICE) and Reusable EICE development system. The main function in EICE we design are testing and debugging. ...
Ing-Jer Huang, Hsin-Ming Chen, Chung-Fu Kao
ASPDAC
2001
ACM
94views Hardware» more  ASPDAC 2001»
14 years 9 days ago
On speeding up extended finite state machines using catalyst circuitry
We propose a timing optimization technique for a complex finite state machine that consists of not only random logic but also data operators. In such a design, the timing critical...
Shi-Yu Huang
ASPDAC
2001
ACM
82views Hardware» more  ASPDAC 2001»
14 years 9 days ago
Towards the logic defect diagnosis for partial-scan designs
Loical defect diagnosis is a critical yet challenging process in VLSI manufacturing. It involves the identification of the defect spots in a logic IC that fails testing. In the la...
Shi-Yu Huang
ASPDAC
2001
ACM
78views Hardware» more  ASPDAC 2001»
14 years 9 days ago
A new congestion-driven placement algorithm based on cell inflation
Wenting Hou, Hong Yu, Xianlong Hong, Yici Cai, Wei...