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DATE
2004
IEEE
132views Hardware» more  DATE 2004»
14 years 12 days ago
Hybrid Architectural Dynamic Thermal Management
When an application or external environmental conditions cause a chip's cooling capacity to be exceeded, dynamic thermal management (DTM) dynamically reduces the power densit...
Kevin Skadron
DATE
2004
IEEE
126views Hardware» more  DATE 2004»
14 years 12 days ago
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...
Montek Singh, Michael Theobald
DATE
2004
IEEE
158views Hardware» more  DATE 2004»
14 years 12 days ago
Communication Analysis for System-On-Chip Design
In this paper we present an approach for analysis of systems of parallel, communicating processes for SoC design. We present a method to detect communications that synchronize the...
Axel Siebenborn, Oliver Bringmann, Wolfgang Rosens...
DATE
2004
IEEE
136views Hardware» more  DATE 2004»
14 years 12 days ago
Compact Binaries with Code Compression in a Software Dynamic Translator
Embedded software is becoming more flexible and adaptable, which presents new challenges for management of highly constrained system resources. Software dynamic translation is a t...
Stacey Shogan, Bruce R. Childers
DATE
2004
IEEE
154views Hardware» more  DATE 2004»
14 years 12 days ago
Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design
For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an ...
Chulho Shin, Young-Taek Kim, Eui-Young Chung, Kyu-...
DATE
2004
IEEE
144views Hardware» more  DATE 2004»
14 years 12 days ago
Smaller Two-Qubit Circuits for Quantum Communication and Computation
We show how to implement an arbitrary two-qubit unitary operation using any of several quantum gate libraries with small a priori upper bounds on gate counts. In analogy to librar...
Vivek V. Shende, Igor L. Markov, Stephen S. Bulloc...
DATE
2004
IEEE
131views Hardware» more  DATE 2004»
14 years 12 days ago
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures
The increasing complexity of system-on-chip (SOC) integrated circuits has spurred the development of versatile automatic test equipment (ATE) that can simultaneously drive differe...
Anuja Sehgal, Krishnendu Chakrabarty
DATE
2004
IEEE
115views Hardware» more  DATE 2004»
14 years 12 days ago
Aspects of Formal and Graphical Design of a Bus System
This study shows the derivation of a local segmented bus arbiter from an original single segment bus arbiter. The operations are performed in the formal framework of action system...
Tiberiu Seceleanu, Tomi Westerlund
DATE
2004
IEEE
109views Hardware» more  DATE 2004»
14 years 12 days ago
RTL Processor Synthesis for Architecture Exploration and Implementation
Architecture description languages are widely used to perform architecture exploration for application-driven designs, whereas the RT-level is the commonly accepted level for hard...
Oliver Schliebusch, Anupam Chattopadhyay, Rainer L...
DATE
2004
IEEE
110views Hardware» more  DATE 2004»
14 years 12 days ago
Interactive Cosimulation with Partial Evaluation
We present a technique to improve the efficiency of hardware-software cosimulation, using design information known at simulator compile-time. The generic term for such optimizatio...
Patrick Schaumont, Ingrid Verbauwhede