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DATE
2004
IEEE
92views Hardware» more  DATE 2004»
14 years 12 days ago
Optimization of Integrated Spiral Inductors Using Sequential Quadratic Programming
The optimization of integrated spiral inductors has great practical importance. Previous optimization methods used in this field are either too slow or depend on very simplified a...
Yong Zhan, Sachin S. Sapatnekar
DATE
2004
IEEE
139views Hardware» more  DATE 2004»
14 years 12 days ago
Flexible Software Protection Using Hardware/Software Codesign Techniques
A strong level of trust in the software running on an embedded processor is a prerequisite for its widespread deployment in any high-risk system. The expanding field of software p...
Joseph Zambreno, Alok N. Choudhary, Rahul Simha, B...
DATE
2004
IEEE
116views Hardware» more  DATE 2004»
14 years 12 days ago
Full-Chip Multilevel Routing for Power and Signal Integrity
Conventional physical design flow separates the design of power network and signal network. Such a separated approach results in slow design convergence for wire-limited deep sub-...
Jinjun Xiong, Lei He
DATE
2004
IEEE
134views Hardware» more  DATE 2004»
14 years 12 days ago
Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor
ASIC designs for future communication applications cannot be simulated exhaustively. Formal Property Checking is a powerful technology to overcome the limitations of current funct...
Klaus Winkelmann, Hans-Joachim Trylus, Dominik Sto...
DATE
2004
IEEE
134views Hardware» more  DATE 2004»
14 years 12 days ago
Arithmetic Reasoning in DPLL-Based SAT Solving
We propose a new arithmetic reasoning calculus to speed up a SAT solver based on the Davis Putnam Longman Loveland (DPLL) procedure. It is based on an arithmetic bit level descrip...
Markus Wedler, Dominik Stoffel, Wolfgang Kunz
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
14 years 12 days ago
Thermal and Power Integrity Based Power/Ground Networks Optimization
With the increasing power density and heat-dissipation cost of modern VLSI designs, thermal and power integrity has become serious concern. Although the impacts of thermal effects...
Ting-Yuan Wang, Jeng-Liang Tsai, Charlie Chung-Pin...
DATE
2004
IEEE
114views Hardware» more  DATE 2004»
14 years 12 days ago
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
Zhong Wang, Xiaobo Sharon Hu
DATE
2004
IEEE
141views Hardware» more  DATE 2004»
14 years 12 days ago
Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors
Reconfigurable Systems-on-Chip (SoC) consist of large Field-Programmable Gate-Arrays (FPGAs) and standard processors. The reconfigurable logic can be used for application-specific...
Miljan Vuletic, Ludovic Righetti, Laura Pozzi, Pao...
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
14 years 12 days ago
Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology
This paper presents an environment based on SystemC for architecture specification of programmable systems. Making use of the new architecture description language ArchC, able to ...
Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Aze...
DATE
2004
IEEE
144views Hardware» more  DATE 2004»
14 years 12 days ago
Cache-Aware Scratchpad Allocation Algorithm
In the context of portable embedded systems, reducing energy is one of the prime objectives. Most high-end embedded microprocessors include onchip instruction and data caches, alo...
Manish Verma, Lars Wehmeyer, Peter Marwedel