CAV
2006
Springer
14 years 12 days ago
2006
Springer
Abstract. In this paper, we reduce pushdown system (PDS) model checking to a graphtheoretic problem, and apply a fast graph algorithm to improve the running time for model checking...
DATE
2004
IEEE
14 years 12 days ago
2004
IEEE
To alleviate the system performance unpredictability of multitasking applications running on multiprocessor platforms with shared memory hierarchies we propose a task level set ba...
CAV
2006
Springer
14 years 12 days ago
2006
Springer
niques for Fast Predicate Abstraction Shuvendu K. Lahiri , Robert Nieuwenhuis , and Albert Oliveras Abstract. Predicate abstraction is a technique for automatically exfinite-state ...
CAV
2006
Springer
14 years 12 days ago
2006
Springer
We present an approach for applying symmetry reduction techniques to probabilistic model checking, a formal verification method for the quantitative analysis of systems with stocha...
DATE
2004
IEEE
14 years 12 days ago
2004
IEEE
Functional verification is widely acknowledged as a major bottleneck in microprocessor design. While early work on specification driven functional test program generation has prop...
DATE
2004
IEEE
14 years 12 days ago
2004
IEEE
In this paper, we study the net and pin distribution problem for global routing targeting three dimensional packaging layout via System-on-Package (SOP). The routing environment f...
CAV
2006
Springer
14 years 12 days ago
2006
Springer
In automated synthesis, we transform a specification into a system that is guaranteed to satisfy the specification. In spite of the rich theory developed for system synthesis, litt...
CAV
2006
Springer
14 years 12 days ago
2006
Springer
DATE
2004
IEEE
14 years 12 days ago
2004
IEEE
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of ...
DATE
2004
IEEE
14 years 12 days ago
2004
IEEE
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed inter...