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ATVA
2007
Springer
101views Hardware» more  ATVA 2007»
14 years 21 days ago
On-the-Fly Model Checking of Fair Non-repudiation Protocols
A fair non-repudiation protocol should guarantee, (1) when a sender sends a message to a receiver, neither the sender nor the receiver can deny having participated in this communic...
Guoqiang Li, Mizuhito Ogawa
ATVA
2007
Springer
90views Hardware» more  ATVA 2007»
14 years 21 days ago
Efficient Approximate Verification of Promela Models Via Symmetry Markers
We present a new verification technique for Promela which exploits state-space symmetries induced by scalarset values used in a model. The technique involves efficiently computing ...
Dragan Bosnacki, Alastair F. Donaldson, Michael Le...
ASYNC
2007
IEEE
129views Hardware» more  ASYNC 2007»
14 years 21 days ago
Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architec...
Gwen Salaün, Wendelin Serwe, Yvain Thonnart, ...
ASPDAC
2007
ACM
108views Hardware» more  ASPDAC 2007»
14 years 21 days ago
Reduced-Order Wide-Band Interconnect Model Realization using Filter-Based Spline Interpolation
In the paper, we develop a systematic methodology for modeling sampled interconnect frequency response data based on spline interpolation. Through piecewise polynomial interpolatio...
Arthur Nieuwoudt, Mehboob Alam, Yehia Massoud
ASPDAC
2007
ACM
85views Hardware» more  ASPDAC 2007»
14 years 21 days ago
Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes
Li-Chun Lin, Shih-Hao Ou, Tay-Jyi Lin, Siang-Den D...
ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
14 years 21 days ago
Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies
- A Cyclic-CPRS (Column Parity Row Selection) technique is presented to diagnose built-in self tested (BISTed) circuits, even in the presence of many unknowns and transient errors....
Chun-Yi Lee, Hung-Mao Lin, Fang-Min Wang, James Ch...
ASPDAC
2007
ACM
131views Hardware» more  ASPDAC 2007»
14 years 21 days ago
Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign
Deep submicron effects drive the complication in designing chips, as well as in package designs and communications between package and board. As a result, the iterative interface d...
Ren-Jie Lee, Ming-Fang Lai, Hung-Ming Chen
ASPDAC
2007
ACM
140views Hardware» more  ASPDAC 2007»
14 years 21 days ago
An Architecture for Combined Test Data Compression and Abort-on-Fail Test
1 The low throughput at IC (Integrated Circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (Automatic Test Equipment) memory requirements and...
Erik Larsson, Jon Persson
ASPDAC
2007
ACM
156views Hardware» more  ASPDAC 2007»
14 years 21 days ago
Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Archit
- This paper presents a real time programmable irregular Low Density Parity Check (LDPC) Encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for fram...
Zahid Khan, Tughrul Arslan