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ISCAS
1993
IEEE
71views Hardware» more  ISCAS 1993»
14 years 26 days ago
Geometric characterization of series-parallel variable resistor networks
Abstract—The range of operating conditions for a seriesparallelnetworkofvariablelinearresistors, voltagesources, and current sources can be represented as a convex polygon in a T...
Randal E. Bryant, J. D. Tygar, Lawrence P. Huang
ISCAS
1993
IEEE
86views Hardware» more  ISCAS 1993»
14 years 26 days ago
A Generalized Precompiling scheme for Surviving Path Memory Management in Viterbi decoders
The management of the surviving path memory in Viterbi's algorithm is generally performed by Trace-Back or Exchange.Register. A generalized method using precompiled trace-back...
Emmanuel Boutillon, N. Demassieux
ISCAS
1993
IEEE
82views Hardware» more  ISCAS 1993»
14 years 26 days ago
Two-dimensional digital filtering using constant-I/O systolic arrays
We present in this paper systolic arrays with constant number of input/output (I/O) ports for twodimensional (2-D) FIR and IIR filtering. Our design has an array of L × N proces...
Mokhtar Aboelaze, De-Lei Lee, Benjamin W. Wah
ISCAS
1993
IEEE
89views Hardware» more  ISCAS 1993»
14 years 26 days ago
Optimal reactive power dispatch with fuzzy variables
K. H. Abdul-Rahman, S. M. Shahidehpour
ISCA
1993
IEEE
113views Hardware» more  ISCA 1993»
14 years 26 days ago
A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch History
Recent attention to speculative execution as a mechanism for increasing performance of single instruction streams has demanded substantially better branch prediction than what has...
Tse-Yu Yeh, Yale N. Patt
ISCA
1993
IEEE
115views Hardware» more  ISCA 1993»
14 years 26 days ago
Parity Logging Overcoming the Small Write Problem in Redundant Disk Arrays
Parity encoded redundant disk arrays provide highly reliable, cost effective secondary storage with high performance for read accesses and large write accesses. Their performance ...
Daniel Stodolsky, Garth A. Gibson, Mark Holland
ISCA
1993
IEEE
153views Hardware» more  ISCA 1993»
14 years 26 days ago
An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing
Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a writeinvalidate protocol result in invalidation actions that could be elimin...
Per Stenström, Mats Brorsson, Lars Sandberg
ISCA
1993
IEEE
125views Hardware» more  ISCA 1993»
14 years 26 days ago
Evaluation of Mechanisms for Fine-Grained Parallel Programs in the J-Machine and the CM-5
er uses an abstract machine approach to compare the mechanisms of two parallel machines: the J-Machine and the CM-5. High-level parallel programs are translated by a single optimi...
Ellen Spertus, Seth Copen Goldstein, Klaus E. Scha...
ISCA
1993
IEEE
112views Hardware» more  ISCA 1993»
14 years 26 days ago
Working Sets, Cache Sizes, and Node Granularity Issues for Large-Scale Multiprocessors
The distribution of resources among processors, memory and caches is a crucial question faced by designers of large-scale parallel machines. If a machine is to solve problems with...
Edward Rothberg, Jaswinder Pal Singh, Anoop Gupta