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ICCD
1994
IEEE
85views Hardware» more  ICCD 1994»
14 years 26 days ago
A Superassociative Tagged Cache Coherence Directory
Dynamically tagged directories are memory-efficient mechanisms for maintaining cache coherence in sharedmemory multiprocessors. These directories use specialpurpose caches of poin...
David J. Lilja, Shanthi Ambalavanan
ICCD
1994
IEEE
75views Hardware» more  ICCD 1994»
14 years 26 days ago
Techniques for Fast CMOS-based Conditional Sum Adders
Hans Lindkvist, Per Andersson
ICCD
1994
IEEE
142views Hardware» more  ICCD 1994»
14 years 26 days ago
Grammar-Based Optimization of Synthesis Scenarios
Systems for multi-level logic optimization are usually based on a set of specialized, loosely-related transformations which work on a network representation. The sequence of trans...
Andreas Kuehlmann, Lukas P. P. P. van Ginneken
ICCD
1994
IEEE
157views Hardware» more  ICCD 1994»
14 years 26 days ago
Mesh Routing Topologies for Multi-FPGA Systems
There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing devices, and software accelerators. An important part of designing such a sy...
Scott Hauck, Gaetano Borriello, Carl Ebeling
ICCAD
1994
IEEE
114views Hardware» more  ICCAD 1994»
14 years 26 days ago
Performance-driven synthesis of asynchronous controllers
We examine the implications of a new hazard-free combinational logic synthesis method [8], which generates multiplexor trees from binary decision diagrams (BDDs) -- representation...
Kenneth Y. Yun, Bill Lin, David L. Dill, Srinivas ...
ICCAD
1994
IEEE
122views Hardware» more  ICCAD 1994»
14 years 26 days ago
An enhanced flow model for constraint handling in hierarchical multi-view design environments
In this paper we present an enhanced design flow model that increases the capabilities of a CAD framework to support design activities on hierarchical multi-view design descriptio...
Pieter van der Wolf, K. Olav ten Bosch, Alfred van...
ICCAD
1994
IEEE
131views Hardware» more  ICCAD 1994»
14 years 26 days ago
Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
Hannah Honghua Yang, D. F. Wong
ICCAD
1994
IEEE
144views Hardware» more  ICCAD 1994»
14 years 26 days ago
Power analysis of embedded software: a first step towards software power minimization
Embedded computer systems are characterized by the presence of a dedicated processor and the software that runs on it. Power constraints are increasingly becoming the critical com...
Vivek Tiwari, Sharad Malik, Andrew Wolfe
ICCAD
1994
IEEE
80views Hardware» more  ICCAD 1994»
14 years 26 days ago
Folding a stack of equal width components
We consider two versions of the problem of folding a stack of equal width components. In both versions, when a stack is folded, a routing penalty is incurred at the fold. In one v...
Venkat Thanvantri, Sartaj K. Sahni