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ICCAD
1994
IEEE
102views Hardware» more  ICCAD 1994»
14 years 26 days ago
Clock period constrained minimal buffer insertion in clock trees
Gustavo E. Téllez, Majid Sarrafzadeh
ICCAD
1994
IEEE
73views Hardware» more  ICCAD 1994»
14 years 26 days ago
Low power state assignment targeting two-and multi-level logic implementations
Chi-Ying Tsui, Massoud Pedram, Chih-Ang Chen, Alvi...
ICCAD
1994
IEEE
65views Hardware» more  ICCAD 1994»
14 years 26 days ago
Incremental formal design verification
Language containment is a method for design verification that involves checking if the behavior of the system to be verified is a subset of the behavior of the specifications (pro...
Gitanjali Swamy, Robert K. Brayton
ICCAD
1994
IEEE
91views Hardware» more  ICCAD 1994»
14 years 26 days ago
A loosely coupled parallel algorithm for standard cell placement
We present a loosely coupled parallel algorithm for the placement of standard cell integrated circuits. Our algorithm is a derivative of simulated annealing. The implementation of...
Wern-Jieh Sun, Carl Sechen
ICCAD
1994
IEEE
80views Hardware» more  ICCAD 1994»
14 years 26 days ago
Macromodeling of analog circuits for hierarchical circuit design
{ Hierarchy plays a signi cant role in the design of digital and analog circuits. At each level of the hierarchy it becomes essential to evaluate if a sub-block design is feasible ...
Jianfeng Shao, Ramesh Harjani
ICCAD
1994
IEEE
77views Hardware» more  ICCAD 1994»
14 years 26 days ago
A specified delay accomplishing clock router using multiple layers
Mitsuho Seki, Kenji Inoue, Kazuo Kato, Kouki Tsuru...
ICCAD
1994
IEEE
111views Hardware» more  ICCAD 1994»
14 years 26 days ago
On modeling top-down VLSI design
We present an improved data model that reflects the whole VLSI design process including bottom-up and topdown design phases. The kernel of the model is a static version concept th...
Bernd Schürmann, Joachim Altmeyer, Martin Sch...
ICCAD
1994
IEEE
106views Hardware» more  ICCAD 1994»
14 years 26 days ago
On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution
Several industrial FPGA routing architectures have been shown to have no efficient routing algorithms (unless P=NP) [3,4]. Here, we further investigate if the intractability of th...
Yu-Liang Wu, Douglas Chang