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    ISSS
    1996
    IEEE
    94views Hardware» more  ISSS 1996»
    Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification
    14 years 27 days ago
    Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification
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    Luca Benini, Patrick Vuillod, Claudionor Jos&eacut...
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    ISSS
    1996
    IEEE
    122views Hardware» more  ISSS 1996»
    Modeling Multicomputer Task Allocation as a Vector Packing Problem
    14 years 27 days ago
    Modeling Multicomputer Task Allocation as a Vector Packing Problem
    Download  www.cecs.uci.edu
    This paper considers the problem of task allocation for embedded, bus
    James E. Beck, Daniel P. Siewiorek
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    ISSS
    1996
    IEEE
    169views Hardware» more  ISSS 1996»
    The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems
    14 years 27 days ago
    The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems
    Download  www.cecs.uci.edu
    The application range of the embedded computing is going to cover the majority of the market products spanning from consumer electronic, automotive, telecom and process control. F...
    Alessandro Balboni, William Fornaciari, M. Vincenz...
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    ISSS
    1996
    IEEE
    73views Hardware» more  ISSS 1996»
    Layout-Driven RTL Binding Techniques for High-Level Synthesis
    14 years 27 days ago
    Layout-Driven RTL Binding Techniques for High-Level Synthesis
    Download  www.iti.uni-stuttgart.de
    Min Xu, Fadi J. Kurdahi
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    ISSS
    1996
    IEEE
    129views Hardware» more  ISSS 1996»
    Hardware/Software Partitioning with Iterative Improvement Heuristics
    14 years 27 days ago
    Hardware/Software Partitioning with Iterative Improvement Heuristics
    Download  www.cecs.uci.edu
    The paper presents two heuristics for hardware/software partitioning of system level specifications. The main objective is to achieve performance optimization with a limited hardw...
    Petru Eles, Zebo Peng, Krzysztof Kuchcinski, Alex ...
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    ISSS
    1996
    IEEE
    103views Hardware» more  ISSS 1996»
    Instruction Set Design and Optimizations for Address Computation in DSP Architectures
    14 years 27 days ago
    Instruction Set Design and Optimizations for Address Computation in DSP Architectures
    Download  www.cecs.uci.edu
    In this paper we investigate the problem of code generation for address computation for DSP processors. This work is divided into four parts. First, we propose a branch instructio...
    Guido Araujo, Ashok Sudarsanam, Sharad Malik
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    ISMVL
    1996
    IEEE
    80views Hardware» more  ISMVL 1996»
    A Literal Gate Using Resonant-Tunneling Devices
    14 years 27 days ago
    A Literal Gate Using Resonant-Tunneling Devices
    Download  www.ntt.co.jp
    Takao Waho, Kevin J. Chen, Masafumi Yamamoto
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    ISMVL
    1996
    IEEE
    76views Hardware» more  ISMVL 1996»
    A Multiple-Valued Ferroelectric Content-Addressable Memory
    14 years 27 days ago
    A Multiple-Valued Ferroelectric Content-Addressable Memory
    Download  www.eecg.toronto.edu
    A novel architecturefor a Multiple-Valued Ferroelectric Content-Addressable Memory (FCAM) is proposed. An FCAM employs ferroelectric capacitors as storage elements to provide a no...
    Ali Sheikholeslami, P. Glenn Gulak, Takahiro Hanyu
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    ISMVL
    1996
    IEEE
    71views Hardware» more  ISMVL 1996»
    Testability of Generalized Multiple-Valued Reed-Muller Circuits
    14 years 27 days ago
    Testability of Generalized Multiple-Valued Reed-Muller Circuits
    Download  web.it.kth.se
    Elena Dubrova, Jon C. Muzio
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    ISMVL
    1996
    IEEE
    85views Hardware» more  ISMVL 1996»
    The Incidence Propagation Method
    14 years 27 days ago
    The Incidence Propagation Method
    Download  www.cs.qub.ac.uk
    Weiru Liu
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