ITC
1996
IEEE
14 years 27 days ago
1996
IEEE
common use is the distinction into two (abstract) fault models: A new fault modelling scheme for integrated analogue general the "Single Hard Fault Model (SHFM)" and the ...
ITC
1996
IEEE
14 years 27 days ago
1996
IEEE
Orthogonal scan paths, which follow the path of the data flow, can be used in data path designs to reduce the test overhead -- area, delay and test application time -- by sharing ...
ITC
1996
IEEE
14 years 27 days ago
1996
IEEE
This paper describes test generation for delay faults caused by global process disturbances. The structural and spatial correlation between path delays is used to reduce the numbe...
ITC
1996
IEEE
14 years 27 days ago
1996
IEEE
The P1149.4 mixed-signal boundary scan standard is demonstrated with a CMOS integrated circuit. Design issues and characterization data are presented.
ITC
1996
IEEE
14 years 27 days ago
1996
IEEE
ITC
1996
IEEE
14 years 27 days ago
1996
IEEE
ITC
1996
IEEE
14 years 27 days ago
1996
IEEE
Abstract. In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not comp...
ITC
1996
IEEE
14 years 27 days ago
1996
IEEE
A 25k gate Test Chip was designed and manufactured to evaluate different test methods for scan-designed circuits. The design of the chip, the experiment, and preliminary experimen...
ITC
1996
IEEE
14 years 27 days ago
1996
IEEE
The detectability of delay flaws can be improved by testing CMOS IC's with a very low supply voltage -between 2 and 2.5 times the threshold voltage Vt of the transistors. A d...
ISSS
1996
IEEE
14 years 27 days ago
1996
IEEE
In this paper we present the problem of flow graph balancing for minimizingthe required memory bandwidth. Our goal is to minimize the required memory bandwidth within the given cy...