Sciweavers

MICRO
1996
IEEE
106views Hardware» more  MICRO 1996»
14 years 27 days ago
Optimization of Machine Descriptions for Efficient Use
A machine description facility allows compiler writers to specify machine execution constraints to the optimization and scheduling phases of an instruction-level parallelism (ILP)...
John C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna...
MICRO
1996
IEEE
89views Hardware» more  MICRO 1996»
14 years 27 days ago
Custom-fit Processors: Letting Applications Define Architectures
Joseph A. Fisher, Paolo Faraboschi, Giuseppe Desol...
MICRO
1996
IEEE
110views Hardware» more  MICRO 1996»
14 years 27 days ago
Efficient Path Profiling
Thomas Ball, James R. Larus
EUROCAST
1997
Springer
85views Hardware» more  EUROCAST 1997»
14 years 27 days ago
Turing Universality of Neural Nets (Revisited)
We show how to use recursive function theory to prove Turing universality of finite analog recurrent neural nets, with a piecewise linear sigmoid function as activation function. W...
João Pedro Guerreiro Neto, Hava T. Siegelma...
EUROCAST
1997
Springer
156views Hardware» more  EUROCAST 1997»
14 years 27 days ago
A Computational Model for Visual Size, Location and Movement
The ability to detect object size, location and movement is essential for a visual system in either a biological or man made environment. In this paper we present a model for esti...
Miguel Alemán-Flores, K. Nicholas Leibovic,...
ITC
1996
IEEE
123views Hardware» more  ITC 1996»
14 years 27 days ago
IDDQ Test: Sensitivity Analysis of Scaling
While technology is changing the face of the world, it itself is changing by leaps and bounds; there is a continuing trend to put more functionality on the same piece of silicon. ...
Thomas W. Williams, Robert H. Dennard, Rohit Kapur...
ITC
1996
IEEE
96views Hardware» more  ITC 1996»
14 years 27 days ago
A Roadmap for Boundary-Scan Test Reuse
This paper proposes a Layered Model for boundaryscan testing to help identify opportunities for standardization. Serial Vector Format [1] and an accompanying Application Programmi...
D. Eugene Wedge, Tom Conner
ITC
1996
IEEE
127views Hardware» more  ITC 1996»
14 years 27 days ago
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
This paper presents a low-overhead scheme for built-in self-test of circuits with scan. Complete (100%) fault coverage is obtained without modifying the function logic and without...
Nur A. Touba, Edward J. McCluskey
ITC
1996
IEEE
107views Hardware» more  ITC 1996»
14 years 27 days ago
Digital Integrated Circuit Testing using Transient Signal Analysis
A novel approach to testing CMOS digital circuits is presented that is based on an analysis of IDD switching transients on the supply rails and voltage transients at selected test...
James F. Plusquellic, Donald M. Chiarulli, Steven ...