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ICCAD
1998
IEEE
105views Hardware» more  ICCAD 1998»
14 years 1 months ago
Fanout optimization under a submicron transistor-level delay model
In this paper we present a new fanout optimization algorithm which is particularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class o...
Pasquale Cocchini, Massoud Pedram, Gianluca Piccin...
ICCAD
1998
IEEE
95views Hardware» more  ICCAD 1998»
14 years 1 months ago
Control generation for embedded systems based on composition of modal processes
In traditional distributed embedded system designs, control information is often replicated across several processes and kept coherent by application-specific mechanisms. Conseque...
Pai H. Chou, Ken Hines, Kurt Partridge, Gaetano Bo...
ICCAD
1998
IEEE
74views Hardware» more  ICCAD 1998»
14 years 1 months ago
Synthesis of application specific instructions for embedded DSP software
Hoon Choi, Seung Ho Hwang, Chong-Min Kyung, In-Che...
ICCAD
1998
IEEE
100views Hardware» more  ICCAD 1998»
14 years 1 months ago
Architecture driven circuit partitioning
Chau-Shen Chen, TingTing Hwang, C. L. Liu
ICCAD
1998
IEEE
93views Hardware» more  ICCAD 1998»
14 years 1 months ago
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
This paper considers simultaneous gate and wire sizing for general very large scale integrated (VLSI) circuits under the Elmore delay model. We present a fast and exact algorithm w...
Chung-Ping Chen, Chris C. N. Chu, D. F. Wong
ICCAD
1998
IEEE
66views Hardware» more  ICCAD 1998»
14 years 1 months ago
Tight integration of combinational verification methods
Combinational verification is an important piece of most equivalence checking tools. In the recent past, many combinational verification algorithms have appeared in the literature...
Jerry R. Burch, Vigyan Singhal
ICCAD
1998
IEEE
122views Hardware» more  ICCAD 1998»
14 years 1 months ago
Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits
In this paper, we present results for significantly improving the performance of sequential circuit diagnostic test pattern generation (DATPG). Our improvements are achieved by de...
Vamsi Boppana, W. Kent Fuchs
ICCAD
1998
IEEE
71views Hardware» more  ICCAD 1998»
14 years 1 months ago
Dynamic power management of electronic systems
Luca Benini, Alessandro Bogliolo, Giovanni De Mich...
ICCAD
1998
IEEE
87views Hardware» more  ICCAD 1998»
14 years 1 months ago
Gate-size selection for standard cell libraries
Frederik Beeftink, Prabhakar Kudva, David S. Kung,...
DATE
1998
IEEE
100views Hardware» more  DATE 1998»
14 years 1 months ago
Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs
After write operations, BIST schemes for RAMs relying on signature analysis must compress the entire memory contents to update the reference signature. This paper introduces a new...
Vyacheslav N. Yarmolik, Sybille Hellebrand, Hans-J...