DATE
1998
IEEE
14 years 1 months ago
1998
IEEE
Despite its importance, we find that a rigorous theoretical foundation for performing timing analysis has been lacking so far. As a result, we have initiated a research project th...
DATE
1998
IEEE
14 years 1 months ago
1998
IEEE
This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectiv...
DATE
1998
IEEE
14 years 1 months ago
1998
IEEE
We propose a new approach to RT-level power modeling for combinationalmacros, that does not require simulationbased characterization. A pattern-dependent power model for a macro i...
DATE
1998
IEEE
14 years 1 months ago
1998
IEEE
This paper presents a new approach to cross-level hierarchical high-level synthesis. A methodology is presented, that supports the efficient synthesis of hierarchical specified sy...
DATE
1998
IEEE
14 years 1 months ago
1998
IEEE
The power dissipated by system-level buses is the largest contribution to the global power of complex VLSI circuits. Therefore, the minimization of the switching activity at the I...
ATS
1998
IEEE
14 years 1 months ago
1998
IEEE
Since Field programmable gate arrays (FPGAs) are reprogrammable, faults in them can be easily toleruted once fault sites are located. Previous researches on diagnosis of FPGAs mai...
ATS
1998
IEEE
14 years 1 months ago
1998
IEEE
A current sensing device, namely Hall Effect MOSFET (HEMOS) is proposed. It is experimentally shown that the HEMOS enables a non-contacting, and non-disturbing current measurement...
ATS
1998
IEEE
14 years 1 months ago
1998
IEEE
In mixed-mode BIST, deterministic test patterns are generated with on-chip hardware to detect the random-pattern-resistant (r.p.r.) faults that are missed by the pseudo-random pat...
ATS
1998
IEEE
14 years 1 months ago
1998
IEEE
We propose a new static test set compaction method based on a careful examination of attributes of fault coverage curves. Our method is based on two key ideas: 1 fault-list and te...
ATS
1998
IEEE
14 years 1 months ago
1998
IEEE
This paper presents the design and simulation method for developing a RISC-based 32-bit embedded on-board computer. Instead of the conventional breadboarded prototype, (1) we used...