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ICCAD
1998
IEEE
112views Hardware» more  ICCAD 1998»
14 years 1 months ago
Using precomputation in architecture and logic resynthesis
Abstract Althoughtremendousadvanceshave been accomplished in logic synthesis in the past two decades, in some cases logic synthesis still cannot attain the improvements possible by...
Soha Hassoun, Carl Ebeling
ICCAD
1998
IEEE
96views Hardware» more  ICCAD 1998»
14 years 1 months ago
Test set compaction algorithms for combinational circuits
This paper presents two new algorithms, Redundant Vector Elimination(RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under th...
Ilker Hamzaoglu, Janak H. Patel
ICCAD
1998
IEEE
98views Hardware» more  ICCAD 1998»
14 years 1 months ago
Determination of worst-case aggressor alignment for delay calculation
Increases in delay due to coupling can have a dramatic impact on IC performance for deep submicron technologies. To achieve maximum performance there is a need for analyzing logic...
Paul D. Gross, Ravishankar Arunachalam, Karthik Ra...
ICCAD
1998
IEEE
70views Hardware» more  ICCAD 1998»
14 years 1 months ago
Verification by approximate forward and backward reachability
Shankar G. Govindaraju, David L. Dill
ICCAD
1998
IEEE
101views Hardware» more  ICCAD 1998»
14 years 1 months ago
Wireplanning in logic synthesis
In this paper, we propose a new logic synthesis methodology to deal with the increasing importance of the interconnect delay in deepsubmicron technologies. We first show that conv...
Wilsin Gosti, Amit Narayan, Robert K. Brayton, Alb...
ICCAD
1998
IEEE
109views Hardware» more  ICCAD 1998»
14 years 1 months ago
CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems
Field programmable gate arrays (FPGAs) are commonly used in embedded systems. Although it is possible to reconfigure some FPGAs while an embedded system is operational, this featu...
Robert P. Dick, Niraj K. Jha
ICCAD
1998
IEEE
95views Hardware» more  ICCAD 1998»
14 years 1 months ago
Efficient analog circuit synthesis with simultaneous yield and robustness optimization
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...
Geert Debyser, Georges G. E. Gielen
ICCAD
1998
IEEE
94views Hardware» more  ICCAD 1998»
14 years 1 months ago
Noise considerations in circuit optimization
Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability e ects. Dynamic logic is partic...
Andrew R. Conn, Ruud A. Haring, Chandramouli Viswe...
ICCAD
1998
IEEE
65views Hardware» more  ICCAD 1998»
14 years 1 months ago
Multiway partitioning with pairwise movement
It is known to many researchers in the partitioning community that the recursive bipartitioning approach outperforms the direct non-recursive approach in solving the multiway part...
Jason Cong, Sung Kyu Lim