Sciweavers

ISCA
2010
IEEE
336views Hardware» more  ISCA 2010»
14 years 1 months ago
Reducing cache power with low-cost, multi-bit error-correcting codes
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chisht...
ISCA
2010
IEEE
176views Hardware» more  ISCA 2010»
14 years 1 months ago
Forwardflow: a scalable core for power-constrained CMPs
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...
Dan Gibson, David A. Wood
ECBS
2010
IEEE
209views Hardware» more  ECBS 2010»
14 years 1 months ago
Continuous Verification of Large Embedded Software Using SMT-Based Bounded Model Checking
The complexity of software in embedded systems has increased significantly over the last years so that software verification now plays an important role in ensuring the overall pr...
Lucas Cordeiro, Bernd Fischer 0002, João Ma...
DATE
2010
IEEE
122views Hardware» more  DATE 2010»
14 years 1 months ago
Optimal regulation of traffic flows in networks-on-chip
We have proposed (, )-based flow regulation to reduce delay and backlog bounds in SoC architectures, where bounds the traffic burstiness and the traffic rate. The regulation is co...
Fahimeh Jafari, Zhonghai Lu, Axel Jantsch, Mohamma...
DATE
2010
IEEE
148views Hardware» more  DATE 2010»
14 years 1 months ago
Scoped identifiers for efficient bit aligned logging
Abstract--Detailed diagnostic data is a prerequisite for debugging problems and understanding runtime performance in distributed wireless embedded systems. Severe bandwidth limitat...
Roy Shea, Mani B. Srivastava, Young Cho
DATE
2010
IEEE
163views Hardware» more  DATE 2010»
14 years 1 months ago
Enhanced Q-learning algorithm for dynamic power management with performance constraint
- This paper presents a novel power management techniques based on enhanced Q-learning algorithms. By exploiting the submodularity and monotonic structure in the cost function of a...
Wei Liu, Ying Tan, Qinru Qiu
DATE
2010
IEEE
190views Hardware» more  DATE 2010»
14 years 1 months ago
Ultra-high throughput string matching for Deep Packet Inspection
Deep Packet Inspection (DPI) involves searching a packet's header and payload against thousands of rules to detect possible attacks. The increase in Internet usage and growing...
Alan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu
DATE
2010
IEEE
163views Hardware» more  DATE 2010»
14 years 1 months ago
Efficient High-Level modeling in the networking domain
-- Starting Electronic System Level (ESL) design flows with executable High-Level Models (HLMs) has the potential to sustainably improve productivity. However, writing good HLMs fo...
Christian Zebelein, Joachim Falk, Christian Haubel...
DATE
2010
IEEE
168views Hardware» more  DATE 2010»
14 years 1 months ago
Verifying UML/OCL models using Boolean satisfiability
Abstract--Nowadays, modeling languages like UML are essential in the design of complex software systems and also start to enter the domain of hardware and hardware/software codesig...
Mathias Soeken, Robert Wille, Mirco Kuhlmann, Mart...