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ASPDAC
1999
ACM
60views Hardware» more  ASPDAC 1999»
14 years 1 months ago
Timing Optimization of Logic Network Using Gate Duplication
We present a timing optimization algorithm based on the concept of gate duplication on the technologydecomposed network. We first examine the relationship between gate duplication...
Chun-hong Chen, Chi-Ying Tsui
ASPDAC
1999
ACM
92views Hardware» more  ASPDAC 1999»
14 years 1 months ago
Hazard-Free Synthesis and Decomposition of Asynchronous Circuits
Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau
ASPDAC
1999
ACM
116views Hardware» more  ASPDAC 1999»
14 years 1 months ago
An Automatic Router for the Pin Grid Array Package
A Pin-Grid-Array (PGA) package router is presented in this paper. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on...
Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chi...
ASPDAC
1999
ACM
65views Hardware» more  ASPDAC 1999»
14 years 1 months ago
Function Smoothing with Applications to VLSI Layout
Ross Baldick, Andrew B. Kahng, Andrew A. Kennings,...
ASPDAC
1999
ACM
132views Hardware» more  ASPDAC 1999»
14 years 1 months ago
Faster and Better Spectral Algorithms for Multi-Way Partitioning
In this paper, two faster and better spectral algorithms are presented for the multi-way circuit partitioning problem with the objective of minimizing the Scaled Cost. As pointed ...
Jan-Yang Chang, Yu-Chen Liu, Ting-Chi Wang
ASPDAC
1999
ACM
76views Hardware» more  ASPDAC 1999»
14 years 1 months ago
Symmetry Detection for Automatic Analog-Layout Recycling
Youcef Bourai, C.-J. Richard Shi
ATS
1999
IEEE
99views Hardware» more  ATS 1999»
14 years 1 months ago
An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets
Abhijit Jas, Kartik Mohanram, Nur A. Touba
ATS
1999
IEEE
103views Hardware» more  ATS 1999»
14 years 1 months ago
Defining SRAM Resistive Defects and Their Simulation Stimuli
A. J. van de Goor, J. E. Simonse
ASYNC
1999
IEEE
67views Hardware» more  ASYNC 1999»
14 years 1 months ago
Relative Timing
Relative Timing is introduced as an informal method for aggressive asynchronous design. It is demonstrated on three example circuits (C-Element, FIFO, and RAPPID Tag Unit), facili...
Ken S. Stevens, Shai Rotem, Ran Ginosar