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DATE
2010
IEEE
156views Hardware» more  DATE 2010»
14 years 2 months ago
Domain specific architecture for next generation wireless communication
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...
Botao Zhang, Hengzhu Liu, Heng Zhao, Fangzheng Mo,...
DATE
2010
IEEE
113views Hardware» more  DATE 2010»
14 years 2 months ago
PM-COSYN: PE and memory co-synthesis for MPSoCs
—Multi-Processor System-on-Chips (MPSoCs) exploit task-level parallelism to achieve high computation throughput, but concurrent memory accesses from multiple PEs may cause memory...
Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang
DATE
2010
IEEE
107views Hardware» more  DATE 2010»
14 years 2 months ago
An error-correcting unordered code and hardware support for robust asynchronous global communication
A new delay-insensitive data encoding scheme for global asynchronous communication is introduced. The goal of this work is to combine the timing-robustness of delay-insensitive (i....
Melinda Y. Agyekum, Steven M. Nowick
DATE
2010
IEEE
132views Hardware» more  DATE 2010»
14 years 2 months ago
Programmable aging sensor for automotive safety-critical applications
- Electronic systems for safety-critical automotive applications must operate for many years in harsh environments. Reliability issues are worsening with device scaling down, while...
Julio César Vázquez, Víctor H...
DATE
2010
IEEE
124views Hardware» more  DATE 2010»
14 years 2 months ago
On the construction of guaranteed passive macromodels for high-speed channels
Abstract—This paper describes a robust and accurate blackbox macromodeling technique, in which the constitutive equations combine both closed-form delay operators and low-order r...
Alessandro Chinea, Stefano Grivet-Talocia, Dirk De...
DATE
2010
IEEE
161views Hardware» more  DATE 2010»
14 years 2 months ago
BISD: Scan-based Built-In self-diagnosis
Abstract—Built-In Self-Test (BIST) is less often applied to random logic than to embedded memories due to the following reasons: Firstly, for a satisfiable fault coverage it may...
Melanie Elm, Hans-Joachim Wunderlich
DATE
2010
IEEE
142views Hardware» more  DATE 2010»
14 years 2 months ago
Testing TSV-based three-dimensional stacked ICs
To meet customer’s product-quality expectations, each individual IC needs to be tested for manufacturing defects incurred during its many high-precision, and hence defect-prone ...
Erik Jan Marinissen
ATS
2009
IEEE
127views Hardware» more  ATS 2009»
14 years 2 months ago
On the Generation of Functional Test Programs for the Cache Replacement Logic
Caches are crucial components in modern processors (both stand-alone or integrated into SoCs) and their test is a challenging task, especially when addressing complex and high-fre...
Wilson J. Perez, Danilo Ravotto, Edgar E. Sá...
ACSD
2009
IEEE
110views Hardware» more  ACSD 2009»
14 years 2 months ago
Variants of the Language Based Synthesis Problem for Petri Nets
The application of synthesis of Petri nets from languages for practical problems has recently attracted increasing attention. However, the classical synthesis problems are often n...
Sebastian Mauser, Robert Lorenz