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IEEEINTERACT
2003
IEEE
14 years 2 months ago
Compiler-Directed Resource Management for Active Code Regions
Recent studies on program execution behavior reveal that a large amount of execution time is spent in small frequently executed regions of code. Whereas adaptive cache management ...
Ravikrishnan Sree, Alex Settle, Ian Bratt, Daniel ...
IEEEINTERACT
2003
IEEE
14 years 2 months ago
The Effect of Compiler Optimizations on Pentium 4 Power Consumption
This paper examines the effect of compiler optimizations on the energy usage and power consumption of the Intel Pentium 4 processor. We measure the effects of different levels of ...
John S. Seng, Dean M. Tullsen
IEEEINTERACT
2003
IEEE
14 years 2 months ago
High Performance Code Generation through Lazy Activation Records
For call intensive programs, function calls are major bottlenecks during program execution since they usually force register contents to be spilled into memory. Such register to m...
Manoranjan Satpathy, Rabi N. Mahapatra, Siddharth ...
IEEEINTERACT
2003
IEEE
14 years 2 months ago
A Region-Based Compilation Infrastructure
: The traditional framework for back-end compilation is based on the scope of functions, which is a natural boundary to partition an entire program for compilation. However, the si...
Yang Liu, Zhaoqing Zhang, Ruliang Qiao, Roy Dz-Chi...
ICCD
2003
IEEE
113views Hardware» more  ICCD 2003»
14 years 2 months ago
Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity
As the technology is shrinking toward 50 nm and the working frequency is going into multi gigahertz range, the effect of interconnects on functionality and performance of system-o...
Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nour...
ICCD
2003
IEEE
143views Hardware» more  ICCD 2003»
14 years 2 months ago
Aggressive Test Power Reduction Through Test Stimuli Transformation
Excessive switching activity during shift cycles in scan-based cores imposes considerable test power challenges. To ensure rapid and reliable test of SOCs, we propose a scan chain...
Ozgur Sinanoglu, Alex Orailoglu
ICCD
2003
IEEE
89views Hardware» more  ICCD 2003»
14 years 2 months ago
Power-Time Tradeoff in Test Scheduling for SoCs
We present a test scheduling methodology for core-based system-on-chips that allows tradeoff between system power dissipation and overall test time. The basic strategy is to use t...
Mehrdad Nourani, James Chin
ICCD
2003
IEEE
104views Hardware» more  ICCD 2003»
14 years 2 months ago
Non-Crossing OBDDs for Mapping to Regular Circuit Structures
In this paper, we propose a novel compact BDD structure, called Non-crossing ordered BDD (NCOBDD), that can be mapped directly to a regular circuit structure. Compared with other ...
Aiqun Cao, Cheng-Kok Koh
ICCAD
2003
IEEE
151views Hardware» more  ICCAD 2003»
14 years 2 months ago
On Compacting Test Response Data Containing Unknown Values
The design of a test response compactor called a Block Compactor is given. Block Compactors belong to a new class of compactors called Finite Memory Compactors. Different from spa...
Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Janu...