Practical mixed-signal DFT solutions are presented with an emphasis on performance, cost, and test coverage. Special consideration is given to the possible DFT techniques for Phas...
This paper presents several important enhancements to the recently published multilevel placement package mPL [12]. The improvements include (i) unconstrained quadratic relaxation...
Tony F. Chan, Jason Cong, Tim Kong, Joseph R. Shin...
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
Two FPGA based implementations of random number generators intended for embedded cryptographic applications are presented. The first is a true random number generator (TRNG) whic...
Kuen Hung Tsoi, K. H. Leung, Philip Heng Wai Leong
A second generation of an embedded input device for kinetically challenged persons is presented. The new system can detect O(n2 ) free motions in space with O(n) hardware, and has...
A module has been implemented in Field Programmable Gate Array (FPGA) hardware that scans the content of Internet packets at Gigabit/second rates. All of the packet processing ope...
James Moscola, John W. Lockwood, Ronald Prescott L...
Most commercial and academic floating point libraries for FPGAs provide only a small fraction of all possible floating point units. In contrast, the floating point unit generat...
A massively parallel single instruction multiple data stream (SIMD) processor designed specifically for cryptographic key search applications is presented. This design aims to ex...
Stanley Y. C. Li, Gap C. K. Cheuk, Kin-Hong Lee, P...