1 This paper presents a method for power-constrained system-on-chip test scheduling in an abort-on-first-fail environment where the test is terminated as soon as a fault is detecte...
Transport Triggered Architecture (TTA) offers a costeffective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. In this pa...
Fabricating large memory and processor arrays is subject to physical failures resulting in yield degradation. The strategy of incorporating spare rows and columns to obtain reason...
Fang Yu, Chung-Hung Tsai, Yao-Wen Huang, D. T. Lee...
Data flow graph dominant designs, such as communication video and audio applications, are common in today’s IC industry. In these designs, the datapath resources (e.g., adders,...
SRAM-based Field Programmable Gate Arrays (FPGAs) are very susceptible to Single Event Upsets (SEUs) that may have dramatic effects on the circuits they implement. In this paper w...
This paper presents a new test methodology which utilizes the Programming Language Interface (PLI) for performing fault simulation of combinational or full scan Intellectual Prope...
Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lom...
The present paper proposes a new method for detecting arbitrary faults in a functional circuit when the set of codewords is limited and known in advance. The method is based on im...
This paper analyzes the deposition defects in devices and circuits made of Quantum-dot Cellular Automata (QCA) for molecular implementation. Differently from metal-based QCA, in ...
Mariam Momenzadeh, Marco Ottavi, Fabrizio Lombardi
A new jitter model is developed using Matlab and Spice to analyze Data Dependent Jitter (DDJ) in serial data integrated circuits. The simulation results show that DDJ is dependent...
As digital imagers grow in pixel count and area, the ability to correct for pixel defects becomes more important. A fault tolerant Active Pixel Sensor (APS) has previously been de...
Cory Jung, Mohammad Hadi Izadi, Michelle L. La Hay...