Sciweavers

DSD
2005
IEEE
106views Hardware» more  DSD 2005»
14 years 2 months ago
Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment
1 This paper presents a method for power-constrained system-on-chip test scheduling in an abort-on-first-fail environment where the test is terminated as soon as a fault is detecte...
Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles
DSD
2005
IEEE
104views Hardware» more  DSD 2005»
14 years 2 months ago
Design of Transport Triggered Architecture Processors for Wireless Encryption
Transport Triggered Architecture (TTA) offers a costeffective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. In this pa...
Panu Hämäläinen, Jari Heikkinen, Ma...
DFT
2005
IEEE
88views VLSI» more  DFT 2005»
14 years 2 months ago
Efficient Exact Spare Allocation via Boolean Satisfiability
Fabricating large memory and processor arrays is subject to physical failures resulting in yield degradation. The strategy of incorporating spare rows and columns to obtain reason...
Fang Yu, Chung-Hung Tsai, Yao-Wen Huang, D. T. Lee...
DFT
2005
IEEE
83views VLSI» more  DFT 2005»
14 years 2 months ago
An ILP Formulation for Yield-driven Architectural Synthesis
Data flow graph dominant designs, such as communication video and audio applications, are common in today’s IC industry. In these designs, the datapath resources (e.g., adders,...
Zhaojun Wo, Israel Koren, Maciej J. Ciesielski
DFT
2005
IEEE
110views VLSI» more  DFT 2005»
14 years 2 months ago
A design flow for protecting FPGA-based systems against single event upsets
SRAM-based Field Programmable Gate Arrays (FPGAs) are very susceptible to Single Event Upsets (SEUs) that may have dramatic effects on the circuits they implement. In this paper w...
Luca Sterpone, Massimo Violante
DFT
2005
IEEE
92views VLSI» more  DFT 2005»
14 years 2 months ago
Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment
This paper presents a new test methodology which utilizes the Programming Language Interface (PLI) for performing fault simulation of combinational or full scan Intellectual Prope...
Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lom...
DFT
2005
IEEE
64views VLSI» more  DFT 2005»
14 years 2 months ago
Implementation of Concurrent Checking Circuits by Independent Sub-circuits
The present paper proposes a new method for detecting arbitrary faults in a functional circuit when the set of codewords is limited and known in advance. The method is based on im...
Vladimir Ostrovsky, Ilya Levin
DFT
2005
IEEE
81views VLSI» more  DFT 2005»
14 years 2 months ago
Modeling QCA Defects at Molecular-level in Combinational Circuits
This paper analyzes the deposition defects in devices and circuits made of Quantum-dot Cellular Automata (QCA) for molecular implementation. Differently from metal-based QCA, in ...
Mariam Momenzadeh, Marco Ottavi, Fabrizio Lombardi
DFT
2005
IEEE
200views VLSI» more  DFT 2005»
14 years 2 months ago
Data Dependent Jitter (DDJ) Characterization Methodology
A new jitter model is developed using Matlab and Spice to analyze Data Dependent Jitter (DDJ) in serial data integrated circuits. The simulation results show that DDJ is dependent...
Kyung Ki Kim, Yong-Bin Kim, Fabrizio Lombardi
DFT
2005
IEEE
81views VLSI» more  DFT 2005»
14 years 2 months ago
Noise Analysis of Fault Tolerant Active Pixel Sensors
As digital imagers grow in pixel count and area, the ability to correct for pixel defects becomes more important. A fault tolerant Active Pixel Sensor (APS) has previously been de...
Cory Jung, Mohammad Hadi Izadi, Michelle L. La Hay...