DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
— This paper suggests a methodology to decrease the power of a static CMOS standard cell design at layout level by focusing on switched capacitance. The term switched is the key:...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
— State of the art statistical timing analysis (STA) tools often yield less accurate results when timing variables become correlated due to global source of variations and path r...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
We present a novel, quality-driven, architectural-level approach that trades-off the output quality to enable power-aware processing of multimedia streams. The error tolerance of ...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
— A novel power attack resistant cryptosystem is presented in this paper. Security in digital computing and communication is becoming increasingly important. Design techniques th...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
A comprehensive probabilistic methodology is proposed to solve the buffer insertion problem with the consideration of process variations. In contrast to a recent work, we point o...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
Context-aware applications pose new challenges, including a need for new computational models, uncertainty management, and efficient optimization under uncertainty. Uncertainty c...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
As Moore’s Law continues to fuel the ability to build ever increasingly complex system-on-chips (SoCs), achieving performance goals is rising as a critical challenge to completi...