— This paper suggests a methodology to decrease the power of a static CMOS standard cell design at layout level by focusing on switched capacitance. The term switched is the key:...
— State of the art statistical timing analysis (STA) tools often yield less accurate results when timing variables become correlated due to global source of variations and path r...
Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chun...
We present a novel, quality-driven, architectural-level approach that trades-off the output quality to enable power-aware processing of multimedia streams. The error tolerance of ...
Shrirang M. Yardi, Michael S. Hsiao, Thomas L. Mar...
— A novel power attack resistant cryptosystem is presented in this paper. Security in digital computing and communication is becoming increasingly important. Design techniques th...
Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan,...
With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of...
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang 000...
A comprehensive probabilistic methodology is proposed to solve the buffer insertion problem with the consideration of process variations. In contrast to a recent work, we point o...
Context-aware applications pose new challenges, including a need for new computational models, uncertainty management, and efficient optimization under uncertainty. Uncertainty c...
Jennifer L. Wong, Weiping Liao, Fei Li, Lei He, Mi...
As Moore’s Law continues to fuel the ability to build ever increasingly complex system-on-chips (SoCs), achieving performance goals is rising as a critical challenge to completi...
Wolf-Dietrich Weber, Joe Chou, Ian Swarbrick, Drew...