In this paper, we present two novel methodologies for testing the interconnect fabrics of network-on-chip (NoC) based chips. Both use the concept of recursive testing, with differ...
This paper presents a new jitter component analysis method for mixed mode VLSI chip testing in Automatic Test Equipment (ATE). The separate components are analyzed individually an...
Kyung Ki Kim, Jing Huang, Yong-Bin Kim, Fabrizio L...
Detection of defective pixels that develop on-line is a vital part of fault tolerant schemes for repairing imagers during operation. This paper presents a new algorithm for the id...
Glenn H. Chapman, Israel Koren, Zahava Koren, Jozs...
Defect and fault tolerance is being studied in a 3D Heterogeneous Sensor using a stacked chip with sensors located on the top plane, and inter-plane vias connecting these to other...
Sequential elements, flip-flops, latches, and memory cells, are the most vulnerable components to soft errors. Since state-of-the-art designs contain millions of bistables, it i...
We propose a novel system-level error tolerance approach specifically targeted for multimedia compression algorithms. In particular we focus on the motion estimation process perf...
In this paper, we propose a system-level error tolerance scheme for systems where a linear transform is combined with quantization. These are key components in multimedia compress...
This paper describes first results from the AutoMoDe (Automotive Model-Based Development) project. The overall goal of the project is to develop an integrated methodology for mode...
Dirk Ziegenbein, Peter Braun 0003, Ulrich Freund, ...