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DATE
2005
IEEE
119views Hardware» more  DATE 2005»
14 years 2 months ago
A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs
This paper proposes a diagnosis scheme aimed at reducing diagnosis time of distributed small embedded SRAMs (e-SRAMs). This scheme improves the one proposed in [7, 8]. The improve...
Baosheng Wang, Yuejian Wu, André Ivanov
DATE
2005
IEEE
108views Hardware» more  DATE 2005»
14 years 2 months ago
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been ide...
Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
DATE
2005
IEEE
139views Hardware» more  DATE 2005»
14 years 2 months ago
EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment Formulation
This paper presents a new mathematical approach to modeling EM wave coupling noise so that it can be easily integrated into chip-level noise analysis tools. The new method employs...
Baohua Wang, Pinaki Mazumder
DATE
2005
IEEE
105views Hardware» more  DATE 2005»
14 years 2 months ago
An Improved Multi-Level Framework for Force-Directed Placement
One of the greatest impediments to achieving high quality placements using force-directed methods lies in the large amount of overlap initially present in these techniques. This o...
Kristofer Vorwerk, Andrew A. Kennings
DATE
2005
IEEE
96views Hardware» more  DATE 2005»
14 years 2 months ago
Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip
In this paper is proposed a technique to integrate and simulate a dynamic memory in a multiprocessor framework based on C/C++/SystemC. Using host machine’s memory management cap...
Oreste Villa, Patrick Schaumont, Ingrid Verbauwhed...
DATE
2005
IEEE
123views Hardware» more  DATE 2005»
14 years 2 months ago
Low Power Oriented CMOS Circuit Optimization Protocol
Alexandre Verle, Xavier Michel, Nadine Azém...
DATE
2005
IEEE
109views Hardware» more  DATE 2005»
14 years 2 months ago
Systematic Analysis of Active Clock Deskewing Systems Using Control Theory
— A formal methodology for the analysis of a closed loop clock distribution and active deskewing network is proposed. In this paper an active clock distribution and deskewing net...
Vinil Varghese, Tom Chen, Peter Michael Young
DATE
2005
IEEE
99views Hardware» more  DATE 2005»
14 years 2 months ago
UML 2 and SysML: An Approach to Deal with Complexity in SoC/NoC Design
UML is gaining increased attention as a system design language, as indicated by current standardization activities such as the SysML initiative and the UML for SoC Forum. Moreover...
Yves Vanderperren, Wim Dehaene
DATE
2005
IEEE
99views Hardware» more  DATE 2005»
14 years 2 months ago
Leakage-Aware Interconnect for On-Chip Network
Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, ...
DATE
2005
IEEE
91views Hardware» more  DATE 2005»
14 years 2 months ago
Reliability-Centric High-Level Synthesis
Importance of addressing soft errors in both safety critical applications and commercial consumer products is increasing, mainly due to ever shrinking geometries, higher-density c...
Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, ...