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MICRO
2006
IEEE
74views Hardware» more  MICRO 2006»
14 years 3 months ago
Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware
Although processor design verification consumes ever-increasing resources, many design defects still slip into production silicon. In a few cases, such bugs have caused expensive...
Smruti R. Sarangi, Abhishek Tiwari, Josep Torrella...
MICRO
2006
IEEE
135views Hardware» more  MICRO 2006»
14 years 3 months ago
Support for High-Frequency Streaming in CMPs
As the industry moves toward larger-scale chip multiprocessors, the need to parallelize applications grows. High inter-thread communication delays, exacerbated by over-stressed hi...
Ram Rangan, Neil Vachharajani, Adam Stoler, Guilhe...
MICRO
2006
IEEE
124views Hardware» more  MICRO 2006»
14 years 3 months ago
LIFT: A Low-Overhead Practical Information Flow Tracking System for Detecting Security Attacks
Computer security is severely threatened by software vulnerabilities. Prior work shows that information flow tracking (also referred to as taint analysis) is a promising techniqu...
Feng Qin, Cheng Wang, Zhenmin Li, Ho-Seop Kim, Yua...
MICRO
2006
IEEE
82views Hardware» more  MICRO 2006»
14 years 3 months ago
Yield-Aware Cache Architectures
One of the major issues faced by the semiconductor industry today is that of reducing chip yields. As the process technologies have scaled to smaller feature sizes, chip yields ha...
Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonath...
MICRO
2006
IEEE
79views Hardware» more  MICRO 2006»
14 years 3 months ago
Fair Queuing Memory Systems
We propose and evaluate a multi-thread memory scheduler that targets high performance CMPs. The proposed memory scheduler is based on concepts originally developed for network fai...
Kyle J. Nesbit, Nidhi Aggarwal, James Laudon, Jame...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 3 months ago
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumpti...
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hs...
MICRO
2006
IEEE
117views Hardware» more  MICRO 2006»
14 years 3 months ago
Coherence Ordering for Ring-based Chip Multiprocessors
Ring interconnects may be an attractive solution for future chip multiprocessors because they can enable faster links than buses and simpler switches than arbitrary switched inter...
Michael R. Marty, Mark D. Hill
MICRO
2006
IEEE
73views Hardware» more  MICRO 2006»
14 years 3 months ago
Merging Head and Tail Duplication for Convergent Hyperblock Formation
VLIW and EDGE (Explicit Data Graph Execution) architectures rely on compilers to form high-quality hyperblocks for good performance. These compilers typically perform hyperblock f...
Bertrand A. Maher, Aaron Smith, Doug Burger, Kathr...
MICRO
2006
IEEE
117views Hardware» more  MICRO 2006»
14 years 3 months ago
PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection
Dynamic software bug detection tools are commonly used because they leverage run-time information. However, they suffer from a fundamental limitation, the Path Coverage Problem: t...
Shan Lu, Pin Zhou, Wei Liu, Yuanyuan Zhou, Josep T...
MICRO
2006
IEEE
115views Hardware» more  MICRO 2006»
14 years 3 months ago
Mitigating the Impact of Process Variations on Processor Register Files and Execution Units
Design variability due to die-to-die and within-die process variations has the potential to significantly reduce the maximum operating frequency and the effective yield of high-p...
Xiaoyao Liang, David Brooks