SBACPAD
2006
IEEE
2006
IEEE
Scalable Parallel Implementation of Bayesian Network to Junction Tree Conversion for Exact Inference
14 years 3 months ago
We present a scalable parallel implementation for converting a Bayesian network to a junction tree, which can then be used for a complete parallel implementation for exact inferen...
SBACPAD
2006
IEEE
14 years 3 months ago
2006
IEEE
SBACPAD
2006
IEEE
14 years 3 months ago
2006
IEEE
SBACPAD
2006
IEEE
14 years 3 months ago
2006
IEEE
Performance evaluation of contemporary processors is becoming increasingly difficult due to the lack of proper frameworks. Traditionally, cycle-accurate simulators have been exte...
SBACPAD
2006
IEEE
14 years 3 months ago
2006
IEEE
Neural-inspired branch predictors achieve very low branch misprediction rates. However, previously proposed implementations have a variety of characteristics that make them challe...
MTV
2006
IEEE
14 years 3 months ago
2006
IEEE
In this paper we will present an optimized structural 01X-SAT-solver for bounded model checking of blackbox designs that exploits semantical knowledge regarding the node selection...
MTV
2006
IEEE
14 years 3 months ago
2006
IEEE
Simulation-based validation of the current industrial processors typically use huge number of test programs generated at instruction set architecture (ISA) level. However, archite...
MTV
2006
IEEE
14 years 3 months ago
2006
IEEE
—Our Mutation-based Validation Paradigm (MVP) is a validation environment for high-level microprocessor implementations. To be able to efficiently generate test sequences, we nee...
MTDT
2006
IEEE
14 years 3 months ago
2006
IEEE
This paper highlights the cell current characterization of a low leakage 6T SRAM by adjusting the threshold voltages of the transistors in the memory array to reduce the standby p...
MTDT
2006
IEEE
14 years 3 months ago
2006
IEEE
We present a ROM compiler programmable from via 1 to via n – 2, where n is the number of metal layers. The layer on which the code via is landed can be selected by the user. Wit...