ISPD
2006
ACM
14 years 3 months ago
2006
ACM
ASPLOS
2006
ACM
14 years 3 months ago
2006
ACM
While the number of transistors on a chip increases exponentially over time, the productivity that can be realized from these systems has not kept pace. To deal with the complexit...
ACMMSP
2006
ACM
14 years 3 months ago
2006
ACM
A blossoming paradigm for block-recursive matrix algorithms is presented that, at once, attains excellent performance measured by • time, • TLB misses, • L1 misses, • L2 m...
ACMMSP
2006
ACM
14 years 3 months ago
2006
ACM
Most operating systems enforce process isolation through hardware protection mechanisms such as memory segmentation, page mapping, and differentiated user and kernel instructions....
ACMMSP
2006
ACM
14 years 3 months ago
2006
ACM
Open nesting provides a loophole in the strict model of atomic transactions. Moss and Hosking suggested adapting open nesting for transactional memory, and Moss and a group at Sta...
ACMMSP
2006
ACM
14 years 3 months ago
2006
ACM
This paper proposes and studies a distributed L2 cache management approach through page-level data to cache slice mapping in a future processor chip comprising many cores. L2 cach...
ACMMSP
2006
ACM
14 years 3 months ago
2006
ACM
We present an implementation and evaluation of atomicity (also known as software transactions) for a dialect of Java. Our implementation is fundamentally different from prior work...
ACMMSP
2006
ACM
14 years 3 months ago
2006
ACM
Stencil-based kernels constitute the core of many scientific applications on block-structured grids. Unfortunately, these codes achieve a low fraction of peak performance, due pr...
ACMMSP
2006
ACM
14 years 3 months ago
2006
ACM
Many people have proposed adding transactions, or atomic blocks, to type-safe high-level programming languages. However, researchers have not considered the semantics of transacti...
SIPS
2006
IEEE
14 years 3 months ago
2006
IEEE
Abstract— This paper presents a design environment for efficiently generating application-specific Intellectual Property (IP) cores for system level signal processing algorithm...