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MICRO
2006
IEEE
104views Hardware» more  MICRO 2006»
14 years 3 months ago
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
Although silicon optical technology is still in its formative stages, and the more near-term application is chip-to-chip communication, rapid advances have been made in the develo...
Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, Jo...
MICRO
2006
IEEE
127views Hardware» more  MICRO 2006»
14 years 3 months ago
A Predictive Performance Model for Superscalar Processors
Designing and optimizing high performance microprocessors is an increasingly difficult task due to the size and complexity of the processor design space, high cost of detailed si...
P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthav...
MICRO
2006
IEEE
111views Hardware» more  MICRO 2006»
14 years 3 months ago
Memory Prefetching Using Adaptive Stream Detection
We present Adaptive Stream Detection, a simple technique for modulating the aggressiveness of a stream prefetcher to match a workload’s observed spatial locality. We use this co...
Ibrahim Hur, Calvin Lin
MICRO
2006
IEEE
155views Hardware» more  MICRO 2006»
14 years 3 months ago
In-Network Cache Coherence
With the trend towards increasing number of processor cores in future chip architectures, scalable directory-based protocols for maintaining cache coherence will be needed. Howeve...
Noel Eisley, Li-Shiuan Peh, Li Shang
MICRO
2006
IEEE
102views Hardware» more  MICRO 2006»
14 years 3 months ago
Managing Distributed, Shared L2 Caches through OS-Level Page Allocation
This paper presents and studies a distributed L2 cache management approach through OS-level page allocation for future many-core processors. L2 cache management is a crucial multi...
Sangyeun Cho, Lei Jin
MICRO
2006
IEEE
100views Hardware» more  MICRO 2006»
14 years 3 months ago
Serialization-Aware Mini-Graphs: Performance with Fewer Resources
Instruction aggregation—the grouping of multiple operations into a single processing unit—is a technique that has recently been used to amplify the bandwidth and capacity of c...
Anne Bracy, Amir Roth
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 3 months ago
ASR: Adaptive Selective Replication for CMP Caches
The large working sets of commercial and scientific workloads stress the L2 caches of Chip Multiprocessors (CMPs). Some CMPs use a shared L2 cache to maximize the on-chip cache c...
Bradford M. Beckmann, Michael R. Marty, David A. W...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 3 months ago
Virtually Pipelined Network Memory
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
Banit Agrawal, Timothy Sherwood
MICRO
2006
IEEE
144views Hardware» more  MICRO 2006»
14 years 3 months ago
Die Stacking (3D) Microarchitecture
3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die ...
Bryan Black, Murali Annavaram, Ned Brekelbaum, Joh...
ISQED
2006
IEEE
136views Hardware» more  ISQED 2006»
14 years 3 months ago
An Improved AMG-based Method for Fast Power Grid Analysis
The continuing VLSI technology scaling leads to increasingly significant power supply fluctuations, which need to be modeled accurately in circuit design and verification. Meanwhi...
Cheng Zhuo, Jiang Hu, Kangsheng Chen