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DFT
2006
IEEE
203views VLSI» more  DFT 2006»
14 years 3 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
DFT
2006
IEEE
99views VLSI» more  DFT 2006»
14 years 3 months ago
Error Tolerance of DNA Self-Assembly by Monomer Concentration Control
Abstract— This paper proposes the control of monomer concentration as a novel improvement of the kinetic Tile Assembly Model (kTAM) to reduce the error rate in DNA selfassembly. ...
Byunghyun Jang, Yong-Bin Kim, Fabrizio Lombardi
DFT
2006
IEEE
130views VLSI» more  DFT 2006»
14 years 3 months ago
Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream
Control flow checking (CFC) is a well known concurrent checking technique for ensuring that a program’s instruction execution sequence follows permissible paths. Almost all CFC...
Federico Rota, Shantanu Dutt, Sahithi Krishna
DFT
2006
IEEE
77views VLSI» more  DFT 2006»
14 years 3 months ago
Fault Tolerant Active Pixel Sensors in 0.18 and 0.35 Micron Technologies
A Fault Tolerant Active Pixel Sensor (FTAPS) has been designed and fabricated to correct for point defects that occur in CMOS image sensors both at manufacturing and over the life...
Michelle L. La Haye, Cory Jung, David Chen, Glenn ...
DFT
2006
IEEE
82views VLSI» more  DFT 2006»
14 years 3 months ago
VLSI Implementation of a Fault-Tolerant Distributed Clock Generation
In this paper we will introduce a novel approach for the on-chip generation of a faulttolerant clock. We will motivate why it becomes more and more desirable to provide VLSI circu...
Markus Ferringer, Gottfried Fuchs, Andreas Steinin...
DFT
2006
IEEE
125views VLSI» more  DFT 2006»
14 years 3 months ago
Synthesis of Efficient Linear Test Pattern Generators
This paper presents a procedure for Synthesis of LINear test pattern Generators called SLING. SLING can synthesize linear test pattern generators that satisfy constraints on area,...
Avijit Dutta, Nur A. Touba
DFT
2006
IEEE
120views VLSI» more  DFT 2006»
14 years 3 months ago
On-Line Mapping of In-Field Defects in Image Sensor Arrays
Continued increase in complexity of digital image sensors means that defects are more likely to develop in the field, but little concrete information is available on in-field defe...
Jozsef Dudas, Cory Jung, Linda Wu, Glenn H. Chapma...
DFT
2006
IEEE
105views VLSI» more  DFT 2006»
14 years 3 months ago
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
1 High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range,...
Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinge...
DFT
2006
IEEE
74views VLSI» more  DFT 2006»
14 years 3 months ago
Recovery Mechanisms for Dual Core Architectures
Dual core architectures are commonly used to establish fault tolerance on the node level. Since comparison is usually performed for the outputs only, no precise diagnostic informa...
Christian El Salloum, Andreas Steininger, Peter Tu...
DDECS
2006
IEEE
101views Hardware» more  DDECS 2006»
14 years 3 months ago
Embedded Built-In-Test Detection Circuit for Radio Frequency Systems and Circuits
: An embedded rectifier-based Built-In-Test (BIT) detection circuit for the RF integrated circuits is proposed in this work, and charge pump rectifier is adopted to transform the R...
Guoyan Zhang, Ronan Farrell