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DDECS
2006
IEEE
106views Hardware» more  DDECS 2006»
14 years 3 months ago
Dynamic Decimal Adder Circuit Design by using the Carry Lookahead
- This paper presents a carry lookahead (CLA) circuitry design based on dynamic circuit aiming at delay reduction in addition of BCD coded decimal numbers. The performance of the p...
Younggap You, Yong-Dae Kim, Jong Hwa Choi
DDECS
2006
IEEE
108views Hardware» more  DDECS 2006»
14 years 3 months ago
Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder
—The impact of shared instruction memory on performance is measured and analyzed for an FPGAbased Multiprocessor System-on-Chip (MP-SoC) with an MPEG-4 video encoding application...
Ari Kulmala, Erno Salminen, Olli Lehtoranta, Timo ...
DDECS
2006
IEEE
88views Hardware» more  DDECS 2006»
14 years 3 months ago
Minimization of Large State Spaces using Symbolic Branching Bisimulation
Abstract: Bisimulations in general are a powerful concept to minimize large finite state systems regarding some well-defined observational behavior. In contrast to strong bisimul...
Ralf Wimmer, Marc Herbstritt, Bernd Becker
DDECS
2006
IEEE
79views Hardware» more  DDECS 2006»
14 years 3 months ago
Multiple-Vector Column-Matching BIST Design Method
- Extension of a BIST design algorithm is proposed in this paper. The method is based on a synthesis of a combinational block - the decoder, transforming pseudo-random code words i...
Petr Fiser, Hana Kubatova
DDECS
2006
IEEE
94views Hardware» more  DDECS 2006»
14 years 3 months ago
A System for Transforming an ANSI C Code with OpenMP Directives into a SystemC Description
Abstract— In this paper, we describe a system for transforming a code given in ANSI C into an equivalent SystemC description. In order to synthesize parallel C codes into hardwar...
Piotr Dziurzanski, W. Bielecki, Konrad Trifunovic,...
DDECS
2006
IEEE
95views Hardware» more  DDECS 2006»
14 years 3 months ago
Parallel Memory Architecture for Arbitrary Stride Accesses
—Parallel memory modules can be used to increase memory bandwidth and feed a processor with only necessary data. Arbitrary stride access capability with interleaved memories is d...
Eero Aho, Jarno Vanne, Timo D. Hämäl&aum...
DATE
2006
IEEE
112views Hardware» more  DATE 2006»
14 years 3 months ago
Simultaneously improving code size, performance, and energy in embedded processors
Code size and energy consumption are critical design concerns for embedded processors as they determine the cost of the overall system. Techniques such as reduced length instructi...
Ahmad Zmily, Christos Kozyrakis
DATE
2006
IEEE
80views Hardware» more  DATE 2006»
14 years 3 months ago
Software-based self-test of processors under power constraints
Software-based self-test (SBST) of processors offers many benefits, such as dispense with expensive test equipments, test execution during maintenance and in the field or initiali...
Jun Zhou, Hans-Joachim Wunderlich
DATE
2006
IEEE
94views Hardware» more  DATE 2006»
14 years 3 months ago
Large power grid analysis using domain decomposition
: This paper presents a domain decomposition (DD) technique for efficient simulation of large-scale linear circuits such as power distribution networks. Simulation results show th...
Quming Zhou, Kai Sun, Kartik Mohanram, Danny C. So...