ICCAD
1998
IEEE
14 years 6 months ago
1998
IEEE
This paper presents a novel concurrent fault simulator (called CONCERT) for nonlinear analog circuits. Three primary techniques in CONCERT, including fault ordering, state predict...
ICCAD
1998
IEEE
14 years 6 months ago
1998
IEEE
We consider the problem of scheduling the mixed workload of both sporadic (on-line) and periodic (off-line) tasks on variable voltage processor to optimize power consumption while...
ICCAD
1998
IEEE
14 years 6 months ago
1998
IEEE
We present a method for optimizing and automating component and transistor sizing for CMOS operational amplifiers. We observe that a wide variety of performance measures can be fo...
ICCAD
1998
IEEE
14 years 6 months ago
1998
IEEE
Presented in this paper are 1) information-theoretic lower bounds on energy consumption of noisy digital gates and 2) the concept of noise tolerance via coding for achieving energy...
ICCAD
1998
IEEE
14 years 6 months ago
1998
IEEE
ICCAD
1998
IEEE
14 years 6 months ago
1998
IEEE
Abstract Althoughtremendousadvanceshave been accomplished in logic synthesis in the past two decades, in some cases logic synthesis still cannot attain the improvements possible by...
ICCAD
1998
IEEE
14 years 6 months ago
1998
IEEE
This paper presents two new algorithms, Redundant Vector Elimination(RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under th...
ICCAD
1998
IEEE
14 years 6 months ago
1998
IEEE
Increases in delay due to coupling can have a dramatic impact on IC performance for deep submicron technologies. To achieve maximum performance there is a need for analyzing logic...
ICCAD
1998
IEEE
14 years 6 months ago
1998
IEEE
ICCAD
1998
IEEE
14 years 6 months ago
1998
IEEE
In this paper, we propose a new logic synthesis methodology to deal with the increasing importance of the interconnect delay in deepsubmicron technologies. We first show that conv...