— As CMOS technology enters the nanometer regime, the increasing process variation is bringing manifest impact on circuit performance. In this paper, we propose a Principle Hessi...
Alexander V. Mitev, Michael Marefat, Dongsheng Ma,...
—This work proposes a new yield computation technique dedicated to HLS, which is an essential component in timing variationaware HLS research field. The SSTAs used by the curren...
— We present a new linear time technique to compute criticality information in a timing graph by dividing it into “zones”. Errors in using tightness probabilities for critica...
Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar,...
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
While the increasing need for addressing process variability in sub-90nm VLSI technologies has sparkled a large body of statistical timing and optimization research, the realizati...
Several technologies with sub-lithographic features are targeting the fabrication of crossbar memories in which the nanowire decoder is playing a major role. In this paper, we sug...
M. Haykel Ben Jamaa, Kirsten E. Moselund, David At...