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ICCAD
2010
IEEE
124views Hardware» more  ICCAD 2010»
13 years 10 months ago
Symbolic performance analysis of elastic systems
Elastic systems, either synchronous or asynchronous, can be optimized for the average-case performance when they have units with early evaluation or variable latency. The performan...
Marc Galceran Oms, Jordi Cortadella, Michael Kishi...
ICCAD
2010
IEEE
126views Hardware» more  ICCAD 2010»
13 years 10 months ago
Characterizing the lifetime reliability of manycore processors with core-level redundancy
With aggressive technology scaling, integrated circuits suffer from everincreasing wearout effects and their lifetime reliability has become a serious concern for the industry. Fo...
Lin Huang, Qiang Xu
ICCAD
2010
IEEE
117views Hardware» more  ICCAD 2010»
13 years 10 months ago
A synthesis flow for digital signal processing with biomolecular reactions
Abstract--We present a methodology for implementing digital signal processing (DSP) operations such as filtering with biomolecular reactions. From a DSP specification, we demonstra...
Hua Jiang, Aleksandra P. Kharam, Marc D. Riedel, K...
ICCAD
2010
IEEE
146views Hardware» more  ICCAD 2010»
13 years 10 months ago
Through-silicon-via management during 3D physical design: When to add and how many?
In 3D integrated circuits through silicon vias (TSVs) are used to connect different dies stacked on top of each other. These TSV occupy silicon area and have significantly larger a...
Mohit Pathak, Young-Joon Lee, Thomas Moon, Sung Ky...
ICCAD
2010
IEEE
140views Hardware» more  ICCAD 2010»
13 years 10 months ago
Polynomial datapath optimization using constraint solving and formal modelling
For a variety of signal processing applications polynomials are implemented in circuits. Recent work on polynomial datapath optimization achieved significant reductions of hardware...
Finn Haedicke, Bijan Alizadeh, Görschwin Fey,...
ICCAD
2010
IEEE
136views Hardware» more  ICCAD 2010»
13 years 10 months ago
Synthesis of an efficient controlling structure for post-silicon clock skew minimization
Clock skew minimization has been an important design constraint. However, due to the complexity of Process, Voltage, and Temperature (PVT) variations, the minimization of clock sk...
Yu-Chien Kao, Hsuan-Ming Chou, Kun-Ting Tsai, Shih...
ICCAD
2010
IEEE
102views Hardware» more  ICCAD 2010»
13 years 10 months ago
Yield enhancement for 3D-stacked memory by redundancy sharing across dies
Three-dimensional (3D) memory products are emerging to fulfill the ever-increasing demands of storage capacity. In 3D-stacked memory, redundancy sharing between neighboring vertic...
Li Jiang, Rong Ye, Qiang Xu
ICCAD
2010
IEEE
139views Hardware» more  ICCAD 2010»
13 years 10 months ago
3D-ICE: Fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling
Categories and Subject Descriptors Keywords .
Arvind Sridhar, Alessandro Vincenzi, Martino Ruggi...
ICCAD
2010
IEEE
121views Hardware» more  ICCAD 2010»
13 years 10 months ago
Multi-Wafer Virtual Probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlation
In this paper, we propose a new technique, referred to as MultiWafer Virtual Probe (MVP) to efficiently model wafer-level spatial variations for nanoscale integrated circuits. Tow...
Wangyang Zhang, Xin Li, Emrah Acar, Frank Liu, Rob...
ICCAD
2010
IEEE
166views Hardware» more  ICCAD 2010»
13 years 10 months ago
Low-power clock trees for CPUs
Clock networks contribute a significant fraction of dynamic power and can be a limiting factor in high-performance CPUs and SoCs. The need for multi-objective optimization over a l...
Dongjin Lee, Myung-Chul Kim, Igor L. Markov