Elastic systems, either synchronous or asynchronous, can be optimized for the average-case performance when they have units with early evaluation or variable latency. The performan...
Marc Galceran Oms, Jordi Cortadella, Michael Kishi...
With aggressive technology scaling, integrated circuits suffer from everincreasing wearout effects and their lifetime reliability has become a serious concern for the industry. Fo...
Abstract--We present a methodology for implementing digital signal processing (DSP) operations such as filtering with biomolecular reactions. From a DSP specification, we demonstra...
Hua Jiang, Aleksandra P. Kharam, Marc D. Riedel, K...
In 3D integrated circuits through silicon vias (TSVs) are used to connect different dies stacked on top of each other. These TSV occupy silicon area and have significantly larger a...
Mohit Pathak, Young-Joon Lee, Thomas Moon, Sung Ky...
For a variety of signal processing applications polynomials are implemented in circuits. Recent work on polynomial datapath optimization achieved significant reductions of hardware...
Clock skew minimization has been an important design constraint. However, due to the complexity of Process, Voltage, and Temperature (PVT) variations, the minimization of clock sk...
Three-dimensional (3D) memory products are emerging to fulfill the ever-increasing demands of storage capacity. In 3D-stacked memory, redundancy sharing between neighboring vertic...
In this paper, we propose a new technique, referred to as MultiWafer Virtual Probe (MVP) to efficiently model wafer-level spatial variations for nanoscale integrated circuits. Tow...
Wangyang Zhang, Xin Li, Emrah Acar, Frank Liu, Rob...
Clock networks contribute a significant fraction of dynamic power and can be a limiting factor in high-performance CPUs and SoCs. The need for multi-objective optimization over a l...