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ICCD
2002
IEEE
109views Hardware» more  ICCD 2002»
14 years 8 months ago
Physical Planning Of On-Chip Interconnect Architectures
Interconnect architecture plays an important role in determining the throughput of meshed communication structures. We assume a mesh structure with uniform communication demand fo...
Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng
ICCD
2002
IEEE
130views Hardware» more  ICCD 2002»
14 years 8 months ago
Branch Behavior of a Commercial OLTP Workload on Intel IA32 Processors
This paper presents a detailed branch characterization of an Oracle based commercial on-line transaction processing workload, Oracle Database Benchmark (ODB), running on an IA32 p...
Murali Annavaram, Trung A. Diep, John Paul Shen
ICCD
2002
IEEE
160views Hardware» more  ICCD 2002»
14 years 8 months ago
Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams
We represent switching activity in VLSI circuits using a graphical probabilistic model based on Cascaded Bayesian Networks (CBN’s). We develop an elegant method for maintaining ...
Sanjukta Bhanja, N. Ranganathan
ICCD
2002
IEEE
101views Hardware» more  ICCD 2002»
14 years 8 months ago
Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input Ordering
Boolean functions are fundamental to synthesis and verification of digital logic, and compact representations of Boolean functions have great practical significance. Popular repre...
Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
ICCD
2002
IEEE
137views Hardware» more  ICCD 2002»
14 years 8 months ago
Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction
Multiple supply voltages, multiple transistor thresholds and transistor sizing could be used to reduce the power dissipation of digital blocks. This paper presents a framework for...
Stephanie Augsburger, Borivoje Nikolic
ICCD
2002
IEEE
135views Hardware» more  ICCD 2002»
14 years 8 months ago
Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip
We present a co-simulation environment for multiprocessor architectures, that is based on SystemC and allows a transparent integration of instruction set simulators (ISSs) within ...
Luca Benini, Davide Bertozzi, Davide Bruni, Nicola...
ICCD
2002
IEEE
110views Hardware» more  ICCD 2002»
14 years 8 months ago
Efficient PEEC-Based Inductance Extraction Using Circuit-Aware Techniques
Practical approaches for on-chip inductance extraction to obtain a sparse, stable and accurate inverse inductance matrix K are proposed. The novelty of our work is in using circui...
Haitian Hu, Sachin S. Sapatnekar
ICCD
2002
IEEE
110views Hardware» more  ICCD 2002»
14 years 8 months ago
Branch Predictor Prediction: A Power-Aware Branch Predictor for High-Performance Processors
We introduce Branch Predictor Prediction (BPP) as a power-aware branch prediction technique for high performance processors. Our predictor reduces branch prediction power dissipat...
Amirali Baniasadi, Andreas Moshovos
ICCD
2002
IEEE
93views Hardware» more  ICCD 2002»
14 years 8 months ago
Speculative Trace Scheduling in VLIW Processors
VLIW processors are statically scheduled processors and their performance depends on the quality of the compiler’s scheduler. We propose a scheduling scheme where the applicatio...
Manvi Agarwal, S. K. Nandy, Jos T. J. van Eijndhov...
ICCD
2002
IEEE
140views Hardware» more  ICCD 2002»
14 years 8 months ago
Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model
— In this paper, we present a new interconnect delay model called Fitted Elmore delay (FED). FED is generated by approximating Hspice delay data using a curve fitting technique....
Arif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Ch...