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ICCD
2005
IEEE
111views Hardware» more  ICCD 2005»
14 years 8 months ago
Low- and Ultra Low-Power Arithmetic Units: Design and Comparison
Design guidelines for low- and ultra low-power arithmetic units are presented. We analyze structures for addition in the energy-delay space to determine the most suitable for thes...
Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdz...
ICCD
2005
IEEE
137views Hardware» more  ICCD 2005»
14 years 8 months ago
Ripple-Precharge TCAM A Low-Power Solution for Network Search Engines
A novel low power ripple-precharge Ternary CAM (RPTCAM) architecture is proposed for applicationsin longest prefix matching tasks. The main motivation behind this research is to ...
Deepak S. Vijayasarathi, Mehrdad Nourani, Mohammad...
ICCD
2005
IEEE
102views Hardware» more  ICCD 2005»
14 years 8 months ago
Monitoring Temperature in FPGA based SoCs
FPGA logic densities continue to increase at a tremendous rate. This has had the undesired consequence of increased power density, which manifests itself as higher ondie temperatu...
Sivakumar Velusamy, Wei Huang, John Lach, Mircea R...
ICCD
2005
IEEE
101views Hardware» more  ICCD 2005»
14 years 8 months ago
Three-Dimensional Cache Design Exploration Using 3DCacti
As technology scales, interconnects dominate the performance and power behavior of deep submicron designs. Three-dimensional integrated circuits (3D ICs) have been proposed as a w...
Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, ...
ICCD
2005
IEEE
135views Hardware» more  ICCD 2005»
14 years 8 months ago
Extended Forward Implications and Dual Recurrence Relations to Identify Sequentially Untestable Faults
In this paper, we make two major contributions: First, to enhance Boolean learning, we propose a new class of logic implications called extended forward implications. Using a nove...
Manan Syal, Rajat Arora, Michael S. Hsiao
ICCD
2005
IEEE
109views Hardware» more  ICCD 2005»
14 years 8 months ago
VALVE: Variable Length Value Encoder for Off-Chip Data Buses.
We propose VAriable Length Value Encoding (VALVE) technique to reduce the power consumption in the off-chip data buses. While past research has focused on encoding fixed length da...
Dinesh C. Suresh, Banit Agrawal, Walid A. Najjar, ...
ICCD
2005
IEEE
98views Hardware» more  ICCD 2005»
14 years 8 months ago
Reducing the Latency and Area Cost of Core Swapping through Shared Helper Engines
Technology scaling trends and the limitations of packaging and cooling have intensified the need for thermally efficient architectures and architecture-level temperature managem...
Anahita Shayesteh, Eren Kursun, Timothy Sherwood, ...
ICCD
2005
IEEE
100views Hardware» more  ICCD 2005»
14 years 8 months ago
Power-Efficient Wakeup Tag Broadcast
The dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The d...
Joseph J. Sharkey, Kanad Ghose, Dmitry V. Ponomare...
ICCD
2005
IEEE
131views Hardware» more  ICCD 2005»
14 years 8 months ago
A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs
The manufacturing test cost for mixed-signal SOCs is widely recognized to be much higher than that for digital SOCs. It has been shown in recent prior work that the use of analog ...
Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
ICCD
2005
IEEE
224views Hardware» more  ICCD 2005»
14 years 8 months ago
Algorithmic and Architectural Design Methodology for Particle Filters in Hardware
In this paper we present algorithmic and architectural methodology for building Particle Filters in hardware. Particle filtering is a new paradigm for filtering in presence of n...
Aswin C. Sankaranarayanan, Rama Chellappa, Ankur S...