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ICCD
2005
IEEE
96views Hardware» more  ICCD 2005»
14 years 8 months ago
File System Interfaces for Embedded Software Development
We present a scalable architectural approach which aims to simplify embedded software development by supporting key development tasks like debugging, tracing and monitoring. Our a...
Bhanu Pisupati, Geoffrey Brown
ICCD
2005
IEEE
121views Hardware» more  ICCD 2005»
14 years 8 months ago
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow
The implementation of interconnect is becoming a significant challenge in modern IC design. Both synchronous and asynchronous strategies have been suggested to manage this problem...
Bradley R. Quinton, Mark R. Greenstreet, Steven J....
ICCD
2005
IEEE
110views Hardware» more  ICCD 2005»
14 years 8 months ago
Implementing Caches in a 3D Technology for High Performance Processors
3D integration is an emergent technology that has the potential to greatly increase device density while simultaneously providing faster on-chip communication. 3D fabrication invo...
Kiran Puttaswamy, Gabriel H. Loh
ICCD
2005
IEEE
101views Hardware» more  ICCD 2005»
14 years 8 months ago
Restrictive Compression Techniques to Increase Level 1 Cache Capacity
Increasing cache latencies limit L1 cache sizes. In this paper we investigate restrictive compression techniques for level 1 data cache, to avoid an increase in the cache access l...
Prateek Pujara, Aneesh Aggarwal
ICCD
2005
IEEE
246views Hardware» more  ICCD 2005»
14 years 8 months ago
H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication
FPGAs (Field-Programmable Gate Arrays) are often used as coprocessors to boost the performance of dataintensive applications [1, 2]. However, mapping algorithms onto multimillion-...
Xizhen Xu, Sotirios G. Ziavras
ICCD
2005
IEEE
108views Hardware» more  ICCD 2005»
14 years 8 months ago
Methods for Modeling Resource Contention on Simultaneous Multithreading Processors
Simultaneous multithreading (SMT) seeks to improve the computation throughput of a processor core by sharing primary resources such as functional units, issue bandwidth, and cache...
Tipp Moseley, Dirk Grunwald, Joshua L. Kihm, Danie...
ICCD
2005
IEEE
102views Hardware» more  ICCD 2005»
14 years 8 months ago
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ICCD
2005
IEEE
97views Hardware» more  ICCD 2005»
14 years 8 months ago
Temperature-Sensitive Loop Parallelization for Chip Multiprocessors
In this paper, we present and evaluate three temperature-sensitive loop parallelization strategies for array-intensive applications executed on chip multiprocessors in order to re...
Sri Hari Krishna Narayanan, Guilin Chen, Mahmut T....