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ISCA
2007
IEEE
162views Hardware» more  ISCA 2007»
14 years 6 months ago
BulkSC: bulk enforcement of sequential consistency
While Sequential Consistency (SC) is the most intuitive memory consistency model and the one most programmers likely assume, current multiprocessors do not support it. Instead, th...
Luis Ceze, James Tuck, Pablo Montesinos, Josep Tor...
ISCA
2007
IEEE
143views Hardware» more  ISCA 2007»
14 years 6 months ago
Performance pathologies in hardware transactional memory
Hardware Transactional Memory (HTM) systems reflect choices from three key design dimensions: conflict detection, version management, and conflict resolution. Previously propos...
Jayaram Bobba, Kevin E. Moore, Haris Volos, Luke Y...
ISCA
2007
IEEE
198views Hardware» more  ISCA 2007»
14 years 6 months ago
Making the fast case common and the uncommon case simple in unbounded transactional memory
Hardware transactional memory has great potential to simplify the creation of correct and efficient multithreaded programs, allowing programmers to exploit more effectively the s...
Colin Blundell, Joe Devietti, E. Christopher Lewis...
ISCA
2007
IEEE
90views Hardware» more  ISCA 2007»
14 years 6 months ago
Transparent control independence (TCI)
AL-ZAWAWI, AHMED SAMI. Transparent Control Independence (TCI). (Under the direction of Dr. Eric Rotenberg). Superscalar architectures have been proposed that exploit control indep...
Ahmed S. Al-Zawawi, Vimal K. Reddy, Eric Rotenberg...
ISCA
2007
IEEE
182views Hardware» more  ISCA 2007»
14 years 6 months ago
Configurable isolation: building high availability systems with commodity multi-core processors
High availability is an increasingly important requirement for enterprise systems, often valued more than performance. Systems designed for high availability typically use redunda...
Nidhi Aggarwal, Parthasarathy Ranganathan, Norman ...
ISCA
2007
IEEE
92views Hardware» more  ISCA 2007»
14 years 6 months ago
Rotary router: an efficient architecture for CMP interconnection networks
Pablo Abad, Valentin Puente, José-Án...
ISCA
2007
IEEE
192views Hardware» more  ISCA 2007»
14 years 6 months ago
Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite
The recently released SPEC CPU2006 benchmark suite is expected to be used by computer designers and computer architecture researchers for pre-silicon early design analysis. Partia...
Aashish Phansalkar, Ajay Joshi, Lizy Kurian John
ISCA
2007
IEEE
196views Hardware» more  ISCA 2007»
14 years 6 months ago
Anton, a special-purpose machine for molecular dynamics simulation
The ability to perform long, accurate molecular dynamics (MD) simulations involving proteins and other biological macromolecules could in principle provide answers to some of the ...
David E. Shaw, Martin M. Deneroff, Ron O. Dror, Je...
ISCA
2007
IEEE
120views Hardware» more  ISCA 2007»
14 years 6 months ago
Examining ACE analysis reliability estimates using fault-injection
ACE analysis is a technique to provide an early reliability estimate for microprocessors. ACE analysis couples data from performance models with low level design details to identi...
Nicholas J. Wang, Aqeel Mahesri, Sanjay J. Patel
ISCA
2007
IEEE
167views Hardware» more  ISCA 2007»
14 years 6 months ago
New cache designs for thwarting software cache-based side channel attacks
Software cache-based side channel attacks are a serious new class of threats for computers. Unlike physical side channel attacks that mostly target embedded cryptographic devices,...
Zhenghong Wang, Ruby B. Lee