While Sequential Consistency (SC) is the most intuitive memory consistency model and the one most programmers likely assume, current multiprocessors do not support it. Instead, th...
Luis Ceze, James Tuck, Pablo Montesinos, Josep Tor...
Hardware Transactional Memory (HTM) systems reflect choices from three key design dimensions: conflict detection, version management, and conflict resolution. Previously propos...
Jayaram Bobba, Kevin E. Moore, Haris Volos, Luke Y...
Hardware transactional memory has great potential to simplify the creation of correct and efficient multithreaded programs, allowing programmers to exploit more effectively the s...
Colin Blundell, Joe Devietti, E. Christopher Lewis...
AL-ZAWAWI, AHMED SAMI. Transparent Control Independence (TCI). (Under the direction of Dr. Eric Rotenberg). Superscalar architectures have been proposed that exploit control indep...
Ahmed S. Al-Zawawi, Vimal K. Reddy, Eric Rotenberg...
High availability is an increasingly important requirement for enterprise systems, often valued more than performance. Systems designed for high availability typically use redunda...
Nidhi Aggarwal, Parthasarathy Ranganathan, Norman ...
The recently released SPEC CPU2006 benchmark suite is expected to be used by computer designers and computer architecture researchers for pre-silicon early design analysis. Partia...
The ability to perform long, accurate molecular dynamics (MD) simulations involving proteins and other biological macromolecules could in principle provide answers to some of the ...
David E. Shaw, Martin M. Deneroff, Ron O. Dror, Je...
ACE analysis is a technique to provide an early reliability estimate for microprocessors. ACE analysis couples data from performance models with low level design details to identi...
Software cache-based side channel attacks are a serious new class of threats for computers. Unlike physical side channel attacks that mostly target embedded cryptographic devices,...