ISCA
2007
IEEE
14 years 6 months ago
2007
IEEE
Conventional load/store queues (LSQs) are an impediment to both power-efficient execution in superscalar processors and scaling to large-window designs. In this paper, we propose...
ISCA
2007
IEEE
14 years 6 months ago
2007
IEEE
Due to wire delay scalability and bandwidth limitations inherent in shared buses and dedicated links, packet-switched on-chip interconnection networks are fast emerging as the per...
ISCA
2007
IEEE
14 years 6 months ago
2007
IEEE
Chip multiprocessors (CMPs) are now commonplace, and the number of cores on a CMP is likely to grow steadily. However, in order to harness the additional compute resources of a CM...