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ISPD
2012
ACM
234views Hardware» more  ISPD 2012»
12 years 7 months ago
MAPLE: multilevel adaptive placement for mixed-size designs
We propose a new multilevel framework for large-scale placement called MAPLE that respects utilization constraints, handles movable macros and guides the transition between global...
Myung-Chul Kim, Natarajan Viswanathan, Charles J. ...
ISPD
2006
ACM
79views Hardware» more  ISPD 2006»
14 years 6 months ago
Non-gaussian statistical parameter modeling for SSTA with confidence interval analysis
Lizheng Zhang, Jun Shao, Charlie Chung-Ping Chen
ISPD
2006
ACM
151views Hardware» more  ISPD 2006»
14 years 6 months ago
Robust extraction of spatial correlation
Jinjun Xiong, Vladimir Zolotov, Lei He
ISPD
2006
ACM
90views Hardware» more  ISPD 2006»
14 years 6 months ago
Fast buffer insertion considering process variations
Advanced process technologies call for a proactive consideration of process variations in design to ensure high parametric timing yield. Despite of its popular use in almost any h...
Jinjun Xiong, Lei He
ISPD
2006
ACM
108views Hardware» more  ISPD 2006»
14 years 6 months ago
Statistical clock tree routing for robustness to process variations
Advances in VLSI technology make clock skew more susceptible to process variations. Notwithstanding efficient zero skew routing algorithms, clock skew still limits post-manufactu...
Uday Padmanabhan, Janet Meiling Wang, Jiang Hu
ISPD
2006
ACM
68views Hardware» more  ISPD 2006»
14 years 6 months ago
Solving hard instances of floorplacement
Physical Design of modern systems on chip is extremely challenging. Such digital integrated circuits often contain tens of millions of logic gates, intellectual property blocks, e...
Aaron N. Ng, Igor L. Markov, Rajat Aggarwal, Venky...
ISPD
2006
ACM
103views Hardware» more  ISPD 2006»
14 years 6 months ago
High accurate pattern based precondition method for extremely large power/ground grid analysis
In this paper, we propose more accurate power/ground network circuit model, which consider both via and ground bounce effects to improve the performance estimation accuracy of on-...
Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hon...
ISPD
2006
ACM
83views Hardware» more  ISPD 2006»
14 years 6 months ago
Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs
Shanq-Jang Ruan, Edwin Naroska, Chun-Chih Chen
ISPD
2006
ACM
71views Hardware» more  ISPD 2006»
14 years 6 months ago
Satisfying whitespace requirements in top-down placement
In this invited note we outline several algorithms and features appearing in Capo 10, free open-source software for congestion-driven standard cell placement, mixed-size placement...
Jarrod A. Roy, David A. Papa, Aaron N. Ng, Igor L....