ISQED
2007
IEEE
14 years 7 months ago
2007
IEEE
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
ISQED
2007
IEEE
14 years 7 months ago
2007
IEEE
We present a methodology for the simulation of soft errors targeting future nano-technological devices. This approach efficiently scales the failure rate of individual devices ac...
ISQED
2007
IEEE
14 years 7 months ago
2007
IEEE
For emerging deep-subwavelength lithography technologies (90 nm and following) the data volume and the complexity of Optical Proximity Correction (OPC) have increased dramatically...
ISQED
2007
IEEE
14 years 7 months ago
2007
IEEE
The virtual channel flow control (VCFC) provides an efficient implementation for on-chip networks. However, allocating the virtual channels (VCs) uniformly results in a waste of a...
ISQED
2007
IEEE
14 years 7 months ago
2007
IEEE
Errors caused by tolerance variations and mismatches among components severely degrade the performance of integrated circuits. These random effects in process parameters significa...
ISQED
2007
IEEE
14 years 7 months ago
2007
IEEE
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we use...
ISQED
2007
IEEE
14 years 7 months ago
2007
IEEE
In nanometer regime, the effects of variations are having an increasing impact on the delay and power characteristics of devices as well as the yield of the circuit. Statistical t...
ISQED
2007
IEEE
14 years 7 months ago
2007
IEEE
ISQED
2007
IEEE
14 years 7 months ago
2007
IEEE
ISQED
2007
IEEE
14 years 7 months ago
2007
IEEE
In this paper, we propose a generalized block structure-preserving reduced order interconnect macromodeling method (BSPRIM). Our approach extends structure-preserving model order ...