ISQED
2009
IEEE
14 years 6 months ago
2009
IEEE
— This paper revisits and extends a general linear programming(LP) formulation to exploit multiple knobs such as multi-Lgate footprint-compatible libraries and post-layout Lgateb...
ISQED
2009
IEEE
14 years 6 months ago
2009
IEEE
- Designing a power-gating structure with high performance in the active mode and low leakage and short wakeup time during standby mode is an important and challenging task. This p...
ISQED
2009
IEEE
14 years 6 months ago
2009
IEEE
— Voltage interpolation is a promising post fabrication technique for combating the effects of process variations. The benefits of voltage interpolation are well understood. It...
ISQED
2009
IEEE
14 years 6 months ago
2009
IEEE
As technology advances, the interconnect delay among modules plays dominant role in chip performance. Buffer insertion, as a traditional approach to reduce wire delay in 2D ICs, i...
ISQED
2009
IEEE
14 years 6 months ago
2009
IEEE
A system-level statistical analysis methodology is described that captures the impact of inter- and intra-die process variations for read timing failures in SRAM circuit blocks. U...
ISQED
2009
IEEE
14 years 6 months ago
2009
IEEE
We propose a novel design flow for mismatch and processvariation aware optimization of nanoscale CMOS Active Pixel Sensor (APS) arrays. As a case study, an 8 × 8 APS array is de...
ISQED
2009
IEEE
14 years 6 months ago
2009
IEEE
With technology scaling, the occurrence rate of not only single, but also multiple transients resulting from a single hit is increasing. In this work, we consider the effect of th...
ISQED
2009
IEEE
14 years 6 months ago
2009
IEEE
Electrical Modeling for High Bandwidth IO Link Chirayu Amin, Chandramouli Kashyap ¬ Intel Corp., Hillsboro, OR Prateek Bhansali ¬ Univ. of Minnesota, Mi...
ISQED
2009
IEEE
14 years 6 months ago
2009
IEEE
We present a small-area 10T SRAM cell without half selection problem. As well, the proposed 10T cell achieves a faster access time and low voltage operation. The cell area is redu...
ISQED
2009
IEEE
14 years 6 months ago
2009
IEEE
An on-chip test-and-measurement system with digital interfaces that can perform device-level characterization of large-dense arrays of transistors is demonstrated in 90- and 65-nm...