Sciweavers

CEC
2011
IEEE
12 years 11 months ago
Cost-benefit analysis of using heuristics in ACGP
—Constrained Genetic Programming (CGP) is a method of searching the Genetic Programming search space non-uniformly, giving preferences to certain subspaces according to some heur...
John W. Aleshunas, Cezary Z. Janikow
CACM
2007
88views more  CACM 2007»
13 years 11 months ago
The choice uncertainty principle
: The choice uncertainty principle says that it is impossible to make an unambiguous choice between near-simultaneous events under a deadline. This principle affects the design of ...
Peter J. Denning
IJIT
2004
14 years 27 days ago
Synthesis of Logic Circuits Using Fractional-Order Dynamic Fitness Functions
This paper analyses the performance of a genetic algorithm using a new concept, namely a fractional-order dynamic fitness function, for the synthesis of combinational logic circuit...
Cecília Reis, José António Te...
ISMVL
2010
IEEE
174views Hardware» more  ISMVL 2010»
14 years 4 months ago
Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits
—Fixed-point multiplication architectures are designed and evaluated using a set of logic cells based on a radix-4, quaternary number system. The library of logic circuits is bas...
Satyendra R. Datla, Mitchell A. Thornton
DSN
2002
IEEE
14 years 4 months ago
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to...
Premkishore Shivakumar, Michael Kistler, Stephen W...
ISMVL
2003
IEEE
112views Hardware» more  ISMVL 2003»
14 years 4 months ago
Iterative Symmetry Indices Decomposition for Ternary Logic Synthesis in Three-Dimensional Space
This paper introduces the implementation of the Iterative Symmetry Indices Decomposition (ISID) for the synthesis of ternary threedimensional logic circuits. The synthesis of regu...
Anas Al-Rabadi
IOLTS
2003
IEEE
126views Hardware» more  IOLTS 2003»
14 years 4 months ago
Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits
A methodology for the synthesis of partially selfchecking multilevel logic circuits with low-cost paritybased concurrent error detection (CED) is described. A subset of the inputs...
Kartik Mohanram, Egor S. Sogomonyan, Michael G&oum...
DATE
2007
IEEE
102views Hardware» more  DATE 2007»
14 years 5 months ago
Accurate and scalable reliability analysis of logic circuits
Reliability of logic circuits is emerging as an important concern that may limit the benefits of continued scaling of process technology and the emergence of future technology al...
Mihir R. Choudhury, Kartik Mohanram
ISMVL
2008
IEEE
111views Hardware» more  ISMVL 2008»
14 years 6 months ago
Multiple Valued Logic Using 3-State Quantum Dot Gate FETs
Abstract—This paper presents fundamental logic structures designed using novel quantum dot gate FETs with three-state characteristics. This three-state FET manifests itself as a ...
John A. Chandy, Faquir C. Jain
DATE
2009
IEEE
140views Hardware» more  DATE 2009»
14 years 6 months ago
Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors
Carbon Nanotube Field-Effect Transistors (CNFETs) show big promise as extensions to silicon-CMOS because: 1) Ideal CNFETs can provide significant energy and performance benefits o...
Subhasish Mitra, Jie Zhang, Nishant Patil, Hai Wei