Static timing analyzers need to know the minimum and maximum number of iterations associated with each loop in a real-time program so accurate timing predictions can be obtained. ...
Speculative multithreading (SpMT) architecture can exploit thread-level parallelism that cannot be identified statically. Speedup can be obtained by speculatively executing threa...
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...
One of the major factors that can potentially slow down widespread use of embedded chip multiprocessors is lack of efficient software support. In particular, automated code paral...
Liping Xue, Mahmut T. Kandemir, Guangyu Chen, Tayl...
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...
Mahmut T. Kandemir, Taylan Yemliha, Seung Woo Son,...
This work proposes and evaluates improvements to previously known algorithms for redundancy elimination. Enhanced Scalar Replacement combines two classic techniques, scalar replac...
— As transistor sizes continue to shrink and the number of transistors per chip keeps increasing, chip multiprocessors (CMPs) are becoming a promising alternative to remain on th...
Taylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kan...