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MICRO
2010
IEEE
128views Hardware» more  MICRO 2010»
13 years 9 months ago
Adaptive and Speculative Slack Simulations of CMPs on CMPs
Current trends signal an imminent crisis in the simulation of future CMPs (Chip MultiProcessors). Future micro-architectures will offer more and more thread contexts to execute pa...
Jianwei Chen, Lakshmi Kumar Dabbiru, Daniel Wong, ...
MICRO
2010
IEEE
154views Hardware» more  MICRO 2010»
13 years 9 months ago
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory
High density memory is becoming more important as many execution streams are consolidated onto single chip many-core processors. DRAM is ubiquitous as a main memory technology, but...
Jeffrey Stuecheli, Dimitris Kaseridis, Hillery C. ...
MICRO
2010
IEEE
186views Hardware» more  MICRO 2010»
13 years 9 months ago
SAFER: Stuck-At-Fault Error Recovery for Memories
As technology scaling poses a threat to DRAM scaling due to physical limitations such as limited charge, alternative memory technologies including several emerging non-volatile me...
Nak Hee Seong, Dong Hyuk Woo, Vijayalakshmi Sriniv...
MICRO
2010
IEEE
132views Hardware» more  MICRO 2010»
13 years 9 months ago
Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches
Energy efficiency is a primary concern for microprocessor designers. A very effective approach to improving the energy efficiency of a chip is to lower its supply voltage to very ...
Timothy N. Miller, Renji Thomas, James Dinan, Bruc...
MICRO
2010
IEEE
146views Hardware» more  MICRO 2010»
13 years 9 months ago
The ZCache: Decoupling Ways and Associativity
The ever-increasing importance of main memory latency and bandwidth is pushing CMPs towards caches with higher capacity and associativity. Associativity is typically improved by in...
Daniel Sanchez, Christos Kozyrakis
MICRO
2010
IEEE
134views Hardware» more  MICRO 2010»
13 years 9 months ago
Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors
Guoping Long, Diana Franklin, Susmit Biswas, Pablo...
MICRO
2010
IEEE
119views Hardware» more  MICRO 2010»
13 years 9 months ago
A Predictive Model for Dynamic Microarchitectural Adaptivity Control
Abstract--Adaptive microarchitectures are a promising solution for designing high-performance, power-efficient microprocessors. They offer the ability to tailor computational resou...
Christophe Dubach, Timothy M. Jones, Edwin V. Boni...
MICRO
2010
IEEE
149views Hardware» more  MICRO 2010»
13 years 9 months ago
Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels
Wide Single Instruction, Multiple Thread (SIMT) architectures often require a static allocation of thread groups that are executed in lockstep throughout the entire application ker...
Michael Steffen, Joseph Zambreno
MICRO
2010
IEEE
242views Hardware» more  MICRO 2010»
13 years 9 months ago
ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory
Advanced Synchronization Facility (ASF) is an AMD64 hardware extension for lock-free data structures and transactional memory. It provides a speculative region that atomically exec...
Jae-Woong Chung, Luke Yen, Stephan Diestelhorst, M...
MICRO
2010
IEEE
99views Hardware» more  MICRO 2010»
13 years 9 months ago
ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment
Recently-proposed architectures that continuously operate on atomic blocks of instructions (also called chunks) can boost the programmability and performance of shared-memory mult...
Xuehai Qian, Wonsun Ahn, Josep Torrellas