As DRAM and other charge memories reach scaling limits, resistive memories, such as phase change memory (PCM), may permit continued scaling of main memories. However, while PCM ma...
Benjamin C. Lee, Ping Zhou, Jun Yang 0002, Youtao ...
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...
This paper proposes a cycle accounting architecture for Simultaneous Multithreading (SMT) processors that estimates the execution times for each of the threads had they been execu...
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...