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MICRO
2010
IEEE
167views Hardware» more  MICRO 2010»
13 years 9 months ago
Erasing Core Boundaries for Robust and Configurable Performance
Single-thread performance, reliability and power efficiency are critical design challenges of future multicore systems. Although point solutions have been proposed to address thes...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott ...
MICRO
2010
IEEE
270views Hardware» more  MICRO 2010»
13 years 9 months ago
Many-Thread Aware Prefetching Mechanisms for GPGPU Applications
Abstract-- We consider the problem of how to improve memory latency tolerance in massively multithreaded GPGPUs when the thread-level parallelism of an application is not sufficien...
Jaekyu Lee, Nagesh B. Lakshminarayana, Hyesoon Kim...
MICRO
2010
IEEE
175views Hardware» more  MICRO 2010»
13 years 9 months ago
Efficient Selection of Vector Instructions Using Dynamic Programming
Accelerating program performance via SIMD vector units is very common in modern processors, as evidenced by the use of SSE, MMX, VSE, and VSX SIMD instructions in multimedia, scien...
Rajkishore Barik, Jisheng Zhao, Vivek Sarkar
MICRO
2010
IEEE
130views Hardware» more  MICRO 2010»
13 years 9 months ago
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
Minseon Ahn, Eun Jung Kim
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 9 months ago
Scalable Speculative Parallelization on Commodity Clusters
While clusters of commodity servers and switches are the most popular form of large-scale parallel computers, many programs are not easily parallelized for execution upon them. In...
Hanjun Kim, Arun Raman, Feng Liu, Jae W. Lee, Davi...
MICRO
2010
IEEE
189views Hardware» more  MICRO 2010»
13 years 9 months ago
A Dynamically Adaptable Hardware Transactional Memory
Most Hardware Transactional Memory (HTM) implementations choose fixed version and conflict management policies at design time. While eager HTM systems store transactional state in-...
Marc Lupon, Grigorios Magklis, Antonio Gonzá...
MICRO
2010
IEEE
210views Hardware» more  MICRO 2010»
13 years 9 months ago
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior
In a modern chip-multiprocessor system, memory is a shared resource among multiple concurrently executing threads. The memory scheduling algorithm should resolve memory contention...
Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor H...
MICRO
2010
IEEE
121views Hardware» more  MICRO 2010»
13 years 9 months ago
Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs
Abstract--Emerging many-core chip multiprocessors will integrate dozens of small processing cores with an on-chip interconnect consisting of point-to-point links. The interconnect ...
Michael M. Lee, John Kim, Dennis Abts, Michael R. ...
MICRO
2010
IEEE
238views Hardware» more  MICRO 2010»
13 years 9 months ago
Sampling Dead Block Prediction for Last-Level Caches
Last-level caches (LLCs) are large structures with significant power requirements. They can be quite inefficient. On average, a cache block in a 2MB LRU-managed LLC is dead 86% of ...
Samira Manabi Khan, Yingying Tian, Daniel A. Jimen...
MICRO
2010
IEEE
142views Hardware» more  MICRO 2010»
13 years 9 months ago
Virtual Snooping: Filtering Snoops in Virtualized Multi-cores
Virtualization has been rapidly expanding its applications in numerous server and desktop environments to improve the utilization and manageability of physical systems. Such prolif...
Daehoon Kim, Hwanju Kim, Jaehyuk Huh