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TCAD
2002
13 years 10 months ago
2002
The paper presents a novel strategy aimed at modelling instruction energy consumption of 32-bits microprocessors. Differently from former approaches, the proposed instruction-level...
FAC
2000
13 years 10 months ago
2000
In this paper we present a method of describing microprocessors at different levels of temporal and data abstraction. We consider microprogrammed, pipelined and superscalar proces...
ISLPED
2007
ACM
14 years 16 days ago
2007
ACM
Based on operand delivery, existing microprocessors can be categorized into architected register file (ARF) or physical register file (PRF) machines, both with or without payload ...
EUROPAR
2004
Springer
14 years 2 months ago
2004
Springer
Abstract. Modern microprocessors have sacrificed the exactness of exceptions for improved performance long ago. This is a side effect of reordering instructions so that the micropr...
DFT
2003
IEEE
14 years 4 months ago
2003
IEEE
This paper presents an approach for integrating fault-tolerance techniques into microprocessors by utilizing instruction redundancy as well as time redundancy. Smaller and smaller...
CALCO
2007
Springer
14 years 5 months ago
2007
Springer
Much current work on modelling and verifying microprocessors can accommodate pipelined and superscalar processors. However, superscalar and pipelined processors are no longer state...
3
posts
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5831
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Homepage
Ahmed Assayed
Sr. Test Engineer; currently employed at Medtronic Inc.
BS electrical engineering - Zagazig University - Egypt
MS computer engineering - North Dakota State Unive...