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IAJIT
2010
84views more  IAJIT 2010»
13 years 11 months ago
A Test Procedure for Boundary Scan Circuitry in PLDs and FPGAs
: A test procedure for testing mainly the boundary scan cells, and testing partially the test access port controller in programmable logic devices, and field programmable gate arra...
Bashar Al-Khalifa
CDES
2006
87views Hardware» more  CDES 2006»
14 years 1 months ago
A Configuration Concept for a Massively Parallel FPGA Architecture
Sandeep Kumar, Christof Paar, Jan Pelzl, Gerd Pfei...
ASAP
2004
IEEE
126views Hardware» more  ASAP 2004»
14 years 4 months ago
Hyper-Programmable Architectures for Adaptable Networked Systems
We explain how modern programmable logic devices have capabilities that are well suited for them to assume a central role in the implementation of networked systems, now and in th...
Gordon J. Brebner, Philip James-Roxby, Eric Keller...
FPL
1998
Springer
121views Hardware» more  FPL 1998»
14 years 4 months ago
Reconfigurable PCI-Bus Interface (RPCI)
In this paper the Peripheral Component Interface PCI is presented as a target/master reconfigurable interface, based on Programmable Logic Devices PLDs (the Field Programmable Gate...
A. Abo Shosha, P. Reinhart, F. Rongen
FPL
1999
Springer
95views Hardware» more  FPL 1999»
14 years 4 months ago
FPGA Viruses
Programmable logic is widely used, for applications ranging from eld-upgradable subsystems to advanced uses such as recon gurable computing platforms which are modi able at run-tim...
Ilija Hadzic, Sanjay Udani, Jonathan M. Smith
FPL
2005
Springer
97views Hardware» more  FPL 2005»
14 years 6 months ago
Safe PLD-based Programmable Controllers
In many industrial processes, an incorrect operation can lead to irreparable damage to people, equipment, or the environment. In order to reduce risks, the electronic control syst...
Jacobo Alvarez, Jorge Marcos, Santiago Fernandez
SBCCI
2006
ACM
171views VLSI» more  SBCCI 2006»
14 years 6 months ago
Asynchronous circuit design on reconfigurable devices
This paper presents the design of asynchronous circuits on synchronous FPGAs and CPLDs. Different design styles have been investigated through the implementation of dual-rail full...
R. U. R. Mocho, G. H. Sartori, Renato P. Ribas, An...
DAC
1998
ACM
15 years 1 months ago
Design and Implementation of the NUMAchine Multiprocessor
This paper describes the design and implementation of the NUMAchine multiprocessor. As the market for CC-NUMA multiprocessors expands, this research project provides a timely arch...
A. Grbic, Stephen Dean Brown, S. Caranci, R. Grind...