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CCR
2010
100views more  CCR 2010»
13 years 11 months ago
Towards understanding bugs in open source router software
Software errors and vulnerabilities in core Internet routers have led to several high-profile attacks on the Internet infrastructure and numerous outages. Building an understandin...
Zuoning Yin, Matthew Caesar, Yuanyuan Zhou
BIRTHDAY
2010
Springer
13 years 11 months ago
Model Checking Programmable Router Configurations
Programmable networks offer the ability to customize router behaviour at run time, thus providing new levels of flexibility for network administrators. We have developed a program...
Luca Zanolin, Cecilia Mascolo, Wolfgang Emmerich
CONEXT
2009
ACM
14 years 16 days ago
Virtually eliminating router bugs
Software bugs in routers lead to network outages, security vulnerabilities, and other unexpected behavior. Rather than simply crashing the router, bugs can violate protocol semant...
Eric Keller, Minlan Yu, Matthew Caesar, Jennifer R...
NSDI
2010
14 years 27 days ago
Seamless BGP Migration with Router Grafting
Network operators are under tremendous pressure to make their networks highly reliable to avoid service disruptions. Yet, operators often need to change the network to upgrade fau...
Eric Keller, Jennifer Rexford, Jacobus E. van der ...
GLVLSI
1996
IEEE
115views VLSI» more  GLVLSI 1996»
14 years 3 months ago
A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh
A VLSI implementation of a programmable router schemefor parallel interconnectionnetwork architectures is presented in this paper. The router executes routing
José G. Delgado-Frias, Jabulani Nyathi, Che...
INFOCOM
1998
IEEE
14 years 3 months ago
Routing Lookups in Hardware at Memory Access Speeds
Increased bandwidth in the Internet puts great demands on network routers; for example, to route minimum sized Gigabit Ethernet packets, an IP router must process about packets pe...
Pankaj Gupta, Steven Lin, Nick McKeown
ICS
1999
Tsinghua U.
14 years 3 months ago
Low-level router design and its impact on supercomputer system performance
Supercomputer performance is highly dependent on its interconnection subsystem design. In this paper we study how di erent architectural approaches for router design impact into s...
Valentin Puente, José A. Gregorio, Cruz Izu...
FCCM
1999
IEEE
143views VLSI» more  FCCM 1999»
14 years 3 months ago
Implementation and Evaluation of a Prototype Reconfigurable Router
The evolution of computer networking technology will likely require hardware that is flexible enough to adapt to changing standards while maintaining the highest possible performa...
Jason R. Hess, David C. Lee, Scott J. Harper, Mark...
ASPDAC
1999
ACM
116views Hardware» more  ASPDAC 1999»
14 years 3 months ago
An Automatic Router for the Pin Grid Array Package
A Pin-Grid-Array (PGA) package router is presented in this paper. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on...
Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chi...
IPPS
2000
IEEE
14 years 3 months ago
Switch Scheduling in the Multimedia Router (MMR)
The primary goal of the Multimedia Router (MMR) project is the design and implementation of a router optimized for multimedia applications. The router is targeted for use in clust...
Damon S. Love, Sudhakar Yalamanchili, José ...