Sciweavers

ICPP
2000
IEEE
14 years 4 months ago
Simultaneous Multithreading-Based Routers
This work considers the use of a n S M T (simultaneous multithreading) processor in lieu of the conventional processor(s) in a router and evaluates quantitatively the potential ga...
Kemathat Vibhatavanij, Nian-Feng Tzeng, Angkul Kon...
INFOCOM
2002
IEEE
14 years 4 months ago
SAVE: Source Address Validity Enforcement Protocol
Forcing all IP packets to carry correct source addresses can greatly help network security, attack tracing, and network problem debugging. However, due to asymmetries in toda...
Jun Li, Jelena Mirkovic, Mengqiu Wang, Peter L. Re...
DANCE
2002
IEEE
14 years 4 months ago
Design and Evaluation of a High Performance Dynamically Extensible Router
This paper describes the design, implementation and performance of an open, high performance, dynamically extensible router under development at Washington University in St. Louis...
Fred Kuhns, John D. DeHart, Anshul Kantawala, Ralp...
AINA
2009
IEEE
14 years 4 months ago
Effects of On-path Buffering on TCP Fairness
Keeping router buffering low helps minimise delay (as well as keeping router costs low), whilst increasing buffering minimises loss. This is a trade-off for which there is no sing...
Saleem N. Bhatti, Martin Bateman
MOBICOM
2003
ACM
14 years 4 months ago
DIRAC: a software-based wireless router system
Routers are expected to play an important role in the IPbased wireless data network. Although a substantial number of techniques have been proposed to improve wireless network per...
Petros Zerfos, Gary Zhong, Jerry Cheng, Haiyun Luo...
DATE
2003
IEEE
93views Hardware» more  DATE 2003»
14 years 4 months ago
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip
Managing the complexity of designing chips containing billions of transistors requires decoupling computation from communication. For the communication, scalable and compositional...
Edwin Rijpkema, Kees G. W. Goossens, Andrei Radule...
ISCA
2005
IEEE
119views Hardware» more  ISCA 2005»
14 years 5 months ago
Microarchitecture of a High-Radix Router
Evolving semiconductor and circuit technology has greatly increased the pin bandwidth available to a router chip. In the early 90s, routers were limited to 10Gb/s of pin bandwidth...
John Kim, William J. Dally, Brian Towles, Amit K. ...
INFOCOM
2005
IEEE
14 years 5 months ago
Practical algorithms for performance guarantees in buffered crossbars
— This paper is about high capacity switches and routers that give guaranteed throughput, rate and delay guarantees. Many routers are built using input queueing or combined input...
Shang-Tse Chuang, Sundar Iyer, Nick McKeown
SOFTVIS
2006
ACM
14 years 5 months ago
The Clack graphical router: visualizing network software
We present Clack, a graphical environment for teaching students how Internet routers work and other core networking concepts. Clack is a router written as a Java Applet, and route...
Dan Wendlandt, Martin Casado, Paul Tarjan, Nick Mc...
ISCA
2006
IEEE
151views Hardware» more  ISCA 2006»
14 years 5 months ago
The BlackWidow High-Radix Clos Network
This paper describes the radix-64 folded-Clos network of the Cray BlackWidow scalable vector multiprocessor. We describe the BlackWidow network which scales to 32K processors with...
Steve Scott, Dennis Abts, John Kim, William J. Dal...